📄 seg7decd.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\test\seg7decd.rpt
seg7decd
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 08 DFFE + 0 2 0 8 q2 (:79)
- 2 - A 03 DFFE + 0 1 0 9 q1 (:80)
- 1 - A 03 DFFE + 0 0 0 10 q0 (:81)
- 5 - A 01 OR2 ! 0 3 1 0 :288
- 4 - A 01 OR2 ! 0 3 1 0 :292
- 3 - A 03 OR2 ! 0 3 1 0 :296
- 3 - A 07 OR2 ! 0 3 1 0 :300
- 5 - A 06 OR2 ! 0 3 1 0 :304
- 7 - A 05 OR2 ! 0 3 1 0 :308
- 1 - A 04 OR2 ! 0 3 1 0 :312
- 1 - A 01 OR2 ! 0 3 1 0 :316
- 1 - B 06 AND2 4 0 0 3 :579
- 1 - B 05 OR2 ! 4 0 0 3 :584
- 3 - B 08 AND2 4 0 0 1 :589
- 1 - B 03 OR2 ! 4 0 0 3 :599
- 1 - B 07 AND2 4 0 0 2 :614
- 3 - B 04 AND2 4 0 0 2 :629
- 1 - B 12 OR2 4 0 1 0 :760
- 5 - B 04 AND2 s 3 0 0 2 ~785~1
- 3 - B 10 OR2 4 0 1 0 :809
- 2 - B 08 OR2 0 3 0 1 :854
- 1 - B 08 OR2 s 4 0 0 1 ~856~1
- 5 - B 08 OR2 0 3 1 0 :860
- 2 - B 04 OR2 4 0 0 1 :878
- 1 - B 04 OR2 0 3 0 1 :887
- 1 - B 02 OR2 0 4 0 1 :904
- 7 - B 02 OR2 0 4 1 0 :911
- 1 - B 11 OR2 4 0 1 0 :962
- 4 - B 04 OR2 s 0 3 0 1 ~992~1
- 1 - B 09 OR2 4 0 1 0 :1013
- 3 - B 02 OR2 4 0 0 1 :1036
- 4 - B 02 OR2 s 4 0 0 2 ~1049~1
- 5 - B 02 OR2 0 4 0 1 :1057
- 6 - B 02 AND2 s 3 0 0 2 ~1058~1
- 2 - B 02 OR2 0 4 1 0 :1064
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\test\seg7decd.rpt
seg7decd
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 2/ 96( 2%) 11/ 48( 22%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\test\seg7decd.rpt
seg7decd
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information: e:\test\seg7decd.rpt
seg7decd
** EQUATIONS **
clk : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
-- Node name is ':81' = 'q0'
-- Equation name is 'q0', location is LC1_A3, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':80' = 'q1'
-- Equation name is 'q1', location is LC2_A3, type is buried.
q1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = q0 & !q1
# !q0 & q1;
-- Node name is ':79' = 'q2'
-- Equation name is 'q2', location is LC1_A8, type is buried.
q2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !q0 & q2
# !q1 & q2
# q0 & q1 & !q2;
-- Node name is 'segout0'
-- Equation name is 'segout0', type is output
segout0 = _LC2_B2;
-- Node name is 'segout1'
-- Equation name is 'segout1', type is output
segout1 = _LC1_B9;
-- Node name is 'segout2'
-- Equation name is 'segout2', type is output
segout2 = _LC1_B11;
-- Node name is 'segout3'
-- Equation name is 'segout3', type is output
segout3 = _LC7_B2;
-- Node name is 'segout4'
-- Equation name is 'segout4', type is output
segout4 = _LC5_B8;
-- Node name is 'segout5'
-- Equation name is 'segout5', type is output
segout5 = _LC3_B10;
-- Node name is 'segout6'
-- Equation name is 'segout6', type is output
segout6 = _LC1_B12;
-- Node name is 'segout7'
-- Equation name is 'segout7', type is output
segout7 = GND;
-- Node name is 'selout0'
-- Equation name is 'selout0', type is output
selout0 = !_LC5_A1;
-- Node name is 'selout1'
-- Equation name is 'selout1', type is output
selout1 = !_LC4_A1;
-- Node name is 'selout2'
-- Equation name is 'selout2', type is output
selout2 = !_LC3_A3;
-- Node name is 'selout3'
-- Equation name is 'selout3', type is output
selout3 = !_LC3_A7;
-- Node name is 'selout4'
-- Equation name is 'selout4', type is output
selout4 = !_LC5_A6;
-- Node name is 'selout5'
-- Equation name is 'selout5', type is output
selout5 = !_LC7_A5;
-- Node name is 'selout6'
-- Equation name is 'selout6', type is output
selout6 = !_LC1_A4;
-- Node name is 'selout7'
-- Equation name is 'selout7', type is output
selout7 = !_LC1_A1;
-- Node name is ':288'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ003);
_EQ003 = q0
# q1
# q2;
-- Node name is ':292'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ004);
_EQ004 = !q0
# q1
# q2;
-- Node name is ':296'
-- Equation name is '_LC3_A3', type is buried
!_LC3_A3 = _LC3_A3~NOT;
_LC3_A3~NOT = LCELL( _EQ005);
_EQ005 = q0
# !q1
# q2;
-- Node name is ':300'
-- Equation name is '_LC3_A7', type is buried
!_LC3_A7 = _LC3_A7~NOT;
_LC3_A7~NOT = LCELL( _EQ006);
_EQ006 = !q0
# !q1
# q2;
-- Node name is ':304'
-- Equation name is '_LC5_A6', type is buried
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ007);
_EQ007 = q0
# q1
# !q2;
-- Node name is ':308'
-- Equation name is '_LC7_A5', type is buried
!_LC7_A5 = _LC7_A5~NOT;
_LC7_A5~NOT = LCELL( _EQ008);
_EQ008 = !q0
# q1
# !q2;
-- Node name is ':312'
-- Equation name is '_LC1_A4', type is buried
!_LC1_A4 = _LC1_A4~NOT;
_LC1_A4~NOT = LCELL( _EQ009);
_EQ009 = q0
# !q1
# !q2;
-- Node name is ':316'
-- Equation name is '_LC1_A1', type is buried
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ010);
_EQ010 = !q0
# !q1
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