📄 decode8.rpt
字号:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 0/168( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 8/168( 4%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/16( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\travel\decode8.rpt
decode8
** EQUATIONS **
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC1_B1;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC1_B4;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = !_LC1_B2;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC2_B1;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC1_B3;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC1_B6;
-- Node name is 'seg6'
-- Equation name is 'seg6', type is output
seg6 = _LC1_B5;
-- Node name is 'seg7'
-- Equation name is 'seg7', type is output
seg7 = GND;
-- Node name is '~382~1'
-- Equation name is '~382~1', location is LC3_B2, type is buried.
-- synthesized logic cell
_LC3_B2 = LCELL( _EQ001);
_EQ001 = data0 & data1 & !data3;
-- Node name is ':387'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ002);
_EQ002 = data3
# data0
# !data2;
-- Node name is ':394'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ003);
_EQ003 = !data0 & data1 & !data2 & !data3;
-- Node name is ':406'
-- Equation name is '_LC5_B1', type is buried
!_LC5_B1 = _LC5_B1~NOT;
_LC5_B1~NOT = LCELL( _EQ004);
_EQ004 = data1
# data2
# !data0
# data3;
-- Node name is ':418'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ005);
_EQ005 = !data0 & !data1 & !data2 & !data3;
-- Node name is ':421'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ006);
_EQ006 = !_LC5_B1 & _LC6_B1
# _LC2_B2 & !_LC5_B1
# _LC4_B1;
-- Node name is ':454'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ007);
_EQ007 = data3
# !data2
# data0 & data1
# !data0 & !data1;
-- Node name is ':513'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ008);
_EQ008 = data1 & data3
# data1 & !data2
# data2 & data3
# !data2 & !data3
# !data0 & data3
# !data0 & data1
# !data0 & !data2
# data0 & !data1 & data2
# data0 & !data1 & !data3;
-- Node name is ':520'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ009);
_EQ009 = _LC4_B1
# _LC2_B2 & !_LC5_B1
# _LC3_B1 & !_LC5_B1;
-- Node name is ':553'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ010);
_EQ010 = data1 & data3
# data2 & data3
# !data0 & data3
# !data0 & data1
# !data0 & !data2;
-- Node name is ':586'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ011);
_EQ011 = data3
# !data0 & !data1
# !data1 & data2
# !data0 & data2;
-- Node name is '~613~1'
-- Equation name is '~613~1', location is LC2_B2, type is buried.
-- synthesized logic cell
_LC2_B2 = LCELL( _EQ012);
_EQ012 = _LC1_B2
# !data2 & _LC3_B2;
-- Node name is ':621'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ013);
_EQ013 = data1 & !data2 & !data3
# !data1 & data2 & !data3
# !data0 & data1 & !data3
# !data1 & !data2 & data3;
Project Information e:\travel\decode8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX8000' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,908K
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