📄 controller.rpt
字号:
controller
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 06 OR2 ! 0 2 0 1 |LPM_ADD_SUB:586|addcore:adder|:63
- 7 - A 03 AND2 0 3 0 2 |LPM_ADD_SUB:586|addcore:adder|:67
- 8 - A 03 AND2 ! 0 2 0 1 |LPM_ADD_SUB:696|addcore:adder|pcarry2
- 7 - A 10 AND2 ! 0 2 0 2 |LPM_ADD_SUB:1055|addcore:adder|pcarry2
- 8 - A 10 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1055|addcore:adder|:63
- 5 - A 03 DFFE + 0 3 0 6 counter4 (:30)
- 1 - A 03 DFFE + 0 2 0 8 counter3 (:31)
- 3 - A 05 DFFE + 0 3 0 10 counter2 (:32)
- 1 - A 05 DFFE + 0 3 0 12 counter1 (:33)
- 7 - A 05 DFFE + 0 1 0 10 counter0 (:34)
- 3 - A 02 DFFE + 0 2 0 12 state1 (:35)
- 5 - A 09 DFFE + 0 3 0 16 state0 (:36)
- 5 - A 02 DFFE + 0 3 1 0 leda2 (:37)
- 8 - A 02 DFFE + 0 2 1 0 leda1 (:38)
- 1 - A 04 DFFE + 0 1 1 0 leda0 (:39)
- 1 - A 02 DFFE + 0 3 1 0 ledb2 (:40)
- 7 - A 02 DFFE + 0 4 1 0 ledb1 (:41)
- 6 - A 02 DFFE + 0 1 1 0 ledb0 (:42)
- 6 - A 03 DFFE + 0 4 0 26 Num14 (:43)
- 3 - A 03 DFFE + 0 4 0 13 Num13 (:44)
- 2 - A 05 DFFE + 0 3 0 11 Num12 (:45)
- 4 - A 11 DFFE + 0 2 0 11 Num11 (:46)
- 6 - A 05 DFFE + 0 2 0 13 Num10 (:47)
- 4 - A 03 DFFE + 0 4 0 13 Num24 (:48)
- 5 - A 10 DFFE + 0 4 0 7 Num23 (:49)
- 4 - A 10 DFFE + 0 4 0 9 Num22 (:50)
- 1 - A 10 DFFE + 0 4 0 16 Num21 (:51)
- 6 - A 10 DFFE + 0 3 0 6 Num20 (:52)
- 6 - A 06 DFFE + 0 3 0 3 Num32 (:53)
- 7 - A 06 DFFE + 0 2 0 3 Num31 (:54)
- 3 - A 06 DFFE + 0 2 0 1 Num30 (:55)
- 4 - A 05 DFFE + 0 3 0 2 cnt (:57)
- 5 - A 06 OR2 s 0 4 0 2 ~735~1
- 8 - A 09 OR2 2 2 0 1 :813
- 1 - A 09 OR2 2 2 0 1 :831
- 2 - A 03 OR2 ! 0 4 0 3 :910
- 3 - A 09 OR2 ! 0 4 0 2 :1092
- 6 - A 09 OR2 2 1 0 1 :1225
- 4 - A 09 OR2 2 1 0 1 :1288
- 4 - A 02 AND2 0 2 0 3 :1487
- 2 - A 02 AND2 0 2 0 12 :1503
- 5 - A 05 AND2 s 0 2 0 4 ~1530~1
- 8 - A 05 OR2 s 0 2 0 2 ~1554~1
- 7 - A 09 OR2 0 4 0 1 :1803
- 2 - A 09 OR2 0 4 0 2 :1827
- 4 - B 05 AND2 ! 0 2 1 6 :2058
- 6 - B 08 OR2 ! 0 2 0 7 :2060
- 3 - B 08 OR2 ! 0 4 0 7 :2136
- 6 - B 07 OR2 ! 0 3 0 1 :2233
- 1 - B 10 AND2 s 0 3 0 5 ~2266~1
- 7 - B 08 AND2 0 3 0 1 :2266
- 1 - B 01 OR2 ! 0 2 0 3 :2431
- 4 - B 01 OR2 s 0 4 0 2 ~2455~1
- 7 - B 01 OR2 0 3 0 1 :2455
- 4 - B 07 OR2 0 3 0 1 :2503
- 5 - B 07 OR2 0 4 0 1 :2509
- 7 - B 07 OR2 0 4 0 1 :2515
- 8 - B 07 OR2 0 4 0 1 :2521
- 7 - B 05 AND2 0 2 0 3 :2595
- 2 - B 05 OR2 ! 0 3 0 3 :2606
- 6 - B 10 AND2 0 4 0 2 :2617
- 8 - B 10 OR2 ! 0 4 0 2 :2628
- 2 - B 01 OR2 s ! 0 3 0 2 ~2650~1
- 2 - B 08 OR2 s ! 0 3 0 4 ~2672~1
- 5 - B 05 AND2 ! 0 2 0 2 :2826
- 4 - B 10 OR2 s 0 2 0 2 ~2850~1
- 8 - B 03 OR2 s ! 0 3 0 2 ~2850~2
- 3 - B 10 OR2 0 4 0 1 :2898
- 4 - B 08 OR2 s ! 0 2 0 4 ~2900~1
- 7 - B 10 AND2 0 4 0 1 :2900
- 2 - B 03 OR2 0 4 0 1 :2904
- 5 - B 10 OR2 0 4 0 1 :2918
- 1 - B 08 OR2 s ! 0 3 0 5 ~2990~1
- 3 - B 03 AND2 s 0 4 0 4 ~3012~1
- 7 - B 03 OR2 ! 0 4 0 2 :3023
- 8 - B 08 AND2 s 0 3 0 4 ~3045~1
- 2 - B 10 OR2 s ! 0 2 0 6 ~3067~1
- 3 - B 05 OR2 ! 0 2 0 3 :3221
- 6 - B 03 OR2 s 0 3 0 2 ~3245~1
- 7 - B 12 OR2 0 3 0 1 :3245
- 4 - B 03 AND2 0 3 0 1 :3293
- 5 - B 03 OR2 0 4 0 1 :3299
- 1 - B 03 OR2 0 4 0 1 :3305
- 1 - B 07 OR2 0 4 0 1 :3311
- 6 - B 05 AND2 0 2 1 0 :3366
- 8 - B 05 OR2 0 4 0 1 :3370
- 1 - B 05 OR2 0 3 1 0 :3373
- 1 - B 12 OR2 0 4 0 1 :3379
- 8 - B 12 OR2 0 4 0 1 :3380
- 8 - B 01 OR2 0 4 1 0 :3382
- 5 - B 08 AND2 s 0 3 0 1 ~3391~1
- 2 - B 12 OR2 s 0 3 0 1 ~3391~2
- 3 - B 12 OR2 s 0 4 0 1 ~3391~3
- 4 - B 12 AND2 s 0 3 0 1 ~3391~4
- 5 - B 12 OR2 s 0 4 0 1 ~3391~5
- 5 - B 01 OR2 s 0 4 0 1 ~3391~6
- 6 - B 01 OR2 s 0 3 0 1 ~3391~7
- 3 - B 01 OR2 s 0 4 0 1 ~3391~8
- 6 - B 12 OR2 0 4 1 0 :3391
- 3 - B 07 OR2 0 4 0 1 :3397
- 2 - B 07 OR2 0 3 1 0 :3400
- 5 - A 22 AND2 s 0 3 0 1 ~3408~1
- 1 - A 23 AND2 s 0 4 0 1 ~3408~2
- 5 - A 23 AND2 s 0 4 0 1 ~3408~3
- 6 - A 22 AND2 s 0 4 0 1 ~3408~4
- 7 - A 16 AND2 0 3 1 5 :3408
- 3 - A 16 OR2 ! 0 2 0 2 :3426
- 7 - A 22 OR2 ! 0 2 0 7 :3449
- 4 - A 16 OR2 s ! 0 2 0 1 ~3469~1
- 6 - A 16 OR2 0 4 0 8 :3469
- 3 - A 10 AND2 s 0 2 0 5 ~3615~1
- 4 - A 23 OR2 ! 0 3 0 4 :3780
- 1 - A 22 OR2 s ! 0 4 0 3 ~3804~1
- 6 - A 13 AND2 s 0 3 0 2 ~3804~2
- 2 - A 22 OR2 s ! 0 3 0 3 ~3955~1
- 3 - A 22 AND2 s 0 4 0 3 ~3966~1
- 1 - A 24 OR2 ! 0 3 0 1 :3977
- 4 - A 22 AND2 s 0 3 0 5 ~3999~1
- 3 - A 24 OR2 ! 0 3 0 1 :3999
- 7 - A 23 AND2 0 3 0 1 :4010
- 8 - A 22 OR2 ! 0 4 0 3 :4175
- 4 - A 13 OR2 s ! 0 4 0 3 ~4199~1
- 3 - A 13 OR2 s 0 4 0 2 ~4199~2
- 2 - A 10 AND2 s 0 2 0 3 ~4249~1
- 8 - A 16 AND2 0 2 1 0 :4320
- 1 - A 13 OR2 0 4 1 0 :4329
- 8 - A 13 OR2 0 4 0 1 :4334
- 2 - A 23 AND2 s 0 2 0 2 ~4335~1
- 7 - A 13 OR2 0 4 0 1 :4335
- 5 - A 13 OR2 0 3 1 0 :4338
- 6 - A 23 OR2 s 0 4 0 1 ~4347~1
- 8 - A 23 OR2 s 0 4 0 1 ~4347~2
- 2 - A 13 OR2 s 0 4 0 1 ~4347~3
- 3 - A 23 OR2 0 4 1 0 :4347
- 4 - A 24 AND2 s 0 3 0 1 ~4356~1
- 5 - A 24 OR2 s 0 4 0 1 ~4356~2
- 6 - A 24 OR2 s 0 4 0 1 ~4356~3
- 7 - A 24 OR2 s 0 3 0 1 ~4356~4
- 8 - A 24 OR2 s 0 3 0 1 ~4356~5
- 2 - A 24 OR2 0 4 1 0 :4356
- 8 - A 06 AND2 0 2 1 0 :4491
- 4 - A 06 AND2 0 2 1 0 :4511
- 2 - A 06 OR2 0 3 1 0 :4527
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\travel\controller.rpt
controller
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 31/ 96( 32%) 5/ 48( 10%) 16/ 48( 33%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
B: 13/ 96( 13%) 23/ 48( 47%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\travel\controller.rpt
controller
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 27 clk
Device-Specific Information: e:\travel\controller.rpt
controller
** EQUATIONS **
clk : INPUT;
sa : INPUT;
sb : INPUT;
-- Node name is ':57' = 'cnt'
-- Equation name is 'cnt', location is LC4_A5, type is buried.
cnt = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC2_A2 & _LC2_A9
# _LC1_A9 & _LC2_A2;
-- Node name is ':34' = 'counter0'
-- Equation name is 'counter0', location is LC7_A5, type is buried.
counter0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !counter0 & _LC5_A5;
-- Node name is ':33' = 'counter1'
-- Equation name is 'counter1', location is LC1_A5, type is buried.
counter1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = cnt & !counter0 & counter1 & _LC8_A5
# cnt & counter0 & !counter1 & _LC8_A5;
-- Node name is ':32' = 'counter2'
-- Equation name is 'counter2', location is LC3_A5, type is buried.
counter2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !counter1 & counter2 & _LC5_A5
# !counter0 & counter2 & _LC5_A5
# counter0 & counter1 & !counter2 & _LC5_A5;
-- Node name is ':31' = 'counter3'
-- Equation name is 'counter3', location is LC1_A3, type is buried.
counter3 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = counter3 & _LC5_A5 & !_LC7_A3
# !counter3 & _LC5_A5 & _LC7_A3;
-- Node name is ':30' = 'counter4'
-- Equation name is 'counter4', location is LC5_A3, type is buried.
counter4 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !counter3 & counter4 & _LC5_A5
# counter4 & _LC5_A5 & !_LC7_A3
# counter3 & !counter4 & _LC5_A5 & _LC7_A3;
-- Node name is 'ga'
-- Equation name is 'ga', type is output
ga = leda0;
-- Node name is 'gb'
-- Equation name is 'gb', type is output
gb = ledb0;
-- Node name is ':39' = 'leda0'
-- Equation name is 'leda0', location is LC1_A4, type is buried.
leda0 = DFFE( _LC2_A2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':38' = 'leda1'
-- Equation name is 'leda1', location is LC8_A2, type is buried.
leda1 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = state0 & !state1;
-- Node name is ':37' = 'leda2'
-- Equation name is 'leda2', location is LC5_A2, type is buried.
leda2 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_A2 & state1
# !_LC2_A2 & !state0;
-- Node name is ':42' = 'ledb0'
-- Equation name is 'ledb0', location is LC6_A2, type is buried.
ledb0 = DFFE( _LC4_A2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':41' = 'ledb1'
-- Equation name is 'ledb1', location is LC7_A2, type is buried.
ledb1 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC2_A2 & !_LC4_A2 & state1
# !_LC2_A2 & !_LC4_A2 & !state0;
-- Node name is ':40' = 'ledb2'
-- Equation name is 'ledb2', location is LC1_A2, type is buried.
ledb2 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = state0 & !state1
# _LC2_A2;
-- Node name is 'Num1h0'
-- Equation name is 'Num1h0', type is output
Num1h0 = _LC6_B5;
-- Node name is 'Num1h1'
-- Equation name is 'Num1h1', type is output
Num1h1 = !_LC4_B5;
-- Node name is 'Num1h2'
-- Equation name is 'Num1h2', type is output
Num1h2 = GND;
-- Node name is 'Num1h3'
-- Equation name is 'Num1h3', type is output
Num1h3 = GND;
-- Node name is 'Num1l0'
-- Equation name is 'Num1l0', type is output
Num1l0 = _LC2_B7;
-- Node name is 'Num1l1'
-- Equation name is 'Num1l1', type is output
Num1l1 = _LC6_B12;
-- Node name is 'Num1l2'
-- Equation name is 'Num1l2', type is output
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