📄 mux8.rpt
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Project Information e:\travel\mux8.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/22/2002 13:16:18
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX8
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
mux8 EPF8282ALC84-4 35 4 0 35 16 %
User Pins: 35 4 0
Device-Specific Information: e:\travel\mux8.rpt
mux8
***** Logic for device 'mux8' compiled without errors.
Device: EPF8282ALC84-4
FLEX 8000 Configuration Scheme: Active Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable DCLK Output in User Mode = OFF
Disable Start-Up Time-Out = OFF
Enable JTAG Support = OFF
^
C
O R R R R R R R R R R R R
N E E E E E E E E E E E E
F S S S S S S S S S V * S S S
_ ^ E E E E E E E E E C S E E E
D D R R R R R R R R R C D R R R ^
O C V V V G V V V V V V I O V V V n
N L E y E E N E y y E E E E E N U E E E S
E K D 3 D D D D 0 2 D D D D D T T D D D P
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
a0 | 12 74 | ^MSEL0
d43 | 13 73 | a2
+DATA0 | 14 72 | &d50
d52 | 15 71 | d51
d60 | 16 70 | d53
VCCINT | 17 69 | d61
d62 | 18 68 | GND
d63 | 19 67 | d41
&d71 | 20 66 | d70
d40 | 21 65 | d72
d01 | 22 EPF8282ALC84-4 64 | d73
d02 | 23 63 | d42
d10 | 24 62 | d03
d12 | 25 61 | d11
GND | 26 60 | d13
&d20 | 27 59 | VCCINT
d32 | 28 58 | d21
d33 | 29 57 | d30
d23 | 30 56 | d31
a1 | 31 55 | &d22
^nSTATUS | 32 54 | d00
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
^ R R y R V R R R R R R R R G R R R R G ^
n E E 1 E C E E E E E E E E N E E E E N M
C S S S C S S S S S S S S D S S S S D S
O E E E I E E E E E E E E E E E E E
N R R R N R R R R R R R R R R R R L
F V V V T V V V V V V V V V V V V 1
I E E E E E E E E E E E E E E E
G D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\travel\mux8.rpt
mux8
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 13/24( 54%)
A3 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/24( 37%)
A4 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/24( 29%)
A5 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
B2 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 14/24( 58%)
B6 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/24( 29%)
B7 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/24( 29%)
B11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 37/64 ( 57%)
Total logic cells used: 35/208 ( 16%)
Average fan-in: 3.00/4 ( 75%)
Total fan-in: 105/832 ( 12%)
Total input pins required: 35
Total input I/O cell registers required: 0
Total output pins required: 4
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 2
Total logic cells required: 35
Total flipflops required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Synthesized logic cells: 0/ 208 ( 0%)
Logic Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 Total
A: 7 0 4 3 1 0 0 1 1 1 0 0 0 18
B: 0 8 0 0 0 3 3 0 0 0 1 1 1 17
Total: 7 8 4 3 1 3 3 1 1 1 1 1 1 35
Device-Specific Information: e:\travel\mux8.rpt
mux8
** INPUTS **
Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
12 - - -- INPUT 0 0 0 7 a0
31 - - -- INPUT 0 0 0 7 a1
73 - - -- INPUT 0 0 0 7 a2
54 - - -- INPUT 0 0 0 1 d00
22 - B -- INPUT 0 0 0 1 d01
23 - B -- INPUT 0 0 0 1 d02
62 - B -- INPUT 0 0 0 1 d03
24 - B -- INPUT 0 0 0 1 d10
61 - B -- INPUT 0 0 0 1 d11
25 - B -- INPUT 0 0 0 1 d12
60 - B -- INPUT 0 0 0 1 d13
27 - B -- INPUT 0 0 0 1 d20
58 - B -- INPUT 0 0 0 1 d21
55 - B -- INPUT 0 0 0 1 d22
30 - B -- INPUT 0 0 0 1 d23
57 - B -- INPUT 0 0 0 1 d30
56 - B -- INPUT 0 0 0 1 d31
28 - B -- INPUT 0 0 0 1 d32
29 - B -- INPUT 0 0 0 1 d33
21 - A -- INPUT 0 0 0 1 d40
67 - A -- INPUT 0 0 0 1 d41
63 - B -- INPUT 0 0 0 1 d42
13 - A -- INPUT 0 0 0 1 d43
72 - A -- INPUT 0 0 0 1 d50
71 - A -- INPUT 0 0 0 1 d51
15 - A -- INPUT 0 0 0 1 d52
70 - A -- INPUT 0 0 0 1 d53
16 - A -- INPUT 0 0 0 1 d60
69 - A -- INPUT 0 0 0 1 d61
18 - A -- INPUT 0 0 0 1 d62
19 - A -- INPUT 0 0 0 1 d63
66 - A -- INPUT 0 0 0 1 d70
20 - A -- INPUT 0 0 0 1 d71
65 - A -- INPUT 0 0 0 1 d72
64 - A -- INPUT 0 0 0 1 d73
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\travel\mux8.rpt
mux8
** OUTPUTS **
Fed By Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
3 - - 06 OUTPUT 0 1 0 0 y0
36 - - 02 OUTPUT 0 1 0 0 y1
2 - - 07 OUTPUT 0 1 0 0 y2
8 - - 02 OUTPUT 0 1 0 0 y3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\travel\mux8.rpt
mux8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 2 A 08 AND2 3 0 0 4 :213
- 3 A 01 OR2 2 1 0 1 :216
- 1 A 09 OR2 ! 3 0 0 4 :223
- 1 A 01 OR2 1 2 0 1 :226
- 3 A 10 AND2 3 0 0 4 :233
- 5 A 01 OR2 1 2 0 1 :236
- 1 A 05 AND2 3 0 0 4 :243
- 6 B 02 OR2 1 2 0 1 :246
- 1 B 11 AND2 3 0 0 4 :253
- 7 B 02 OR2 1 2 0 1 :256
- 2 B 12 AND2 3 0 0 4 :263
- 8 B 02 OR2 1 2 0 1 :266
- 7 B 13 AND2 3 0 0 4 :273
- 1 B 02 OR2 1 2 1 0 :276
- 4 A 01 OR2 2 1 0 1 :282
- 6 A 01 OR2 1 2 0 1 :285
- 7 A 01 OR2 1 2 0 1 :288
- 2 A 01 OR2 1 2 0 1 :291
- 2 B 07 OR2 1 2 0 1 :294
- 3 B 07 OR2 1 2 0 1 :297
- 1 B 07 OR2 1 2 1 0 :300
- 2 A 04 OR2 2 1 0 1 :306
- 1 A 04 OR2 1 2 0 1 :309
- 4 A 04 OR2 1 2 0 1 :312
- 5 B 02 OR2 1 2 0 1 :315
- 3 B 02 OR2 1 2 0 1 :318
- 4 B 02 OR2 1 2 0 1 :321
- 2 B 02 OR2 1 2 1 0 :324
- 1 A 03 OR2 2 1 0 1 :330
- 2 A 03 OR2 1 2 0 1 :333
- 3 A 03 OR2 1 2 0 1 :336
- 4 A 03 OR2 1 2 0 1 :339
- 2 B 06 OR2 1 2 0 1 :342
- 3 B 06 OR2 1 2 0 1 :345
- 1 B 06 OR2 1 2 1 0 :348
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\travel\mux8.rpt
mux8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 22/168( 13%) 15/16( 93%) 1/16( 6%) 0/16( 0%)
B: 21/168( 12%) 16/16(100%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/16( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/16( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 1/16( 6%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/16( 6%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/16( 6%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/16( 6%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/16( 6%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/16( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\travel\mux8.rpt
mux8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
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