📄 fdiv32.rpt
字号:
& = Uses single-pin Output Enable
Device-Specific Information: e:\travel\fdiv32.rpt
fdiv32
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 12 OR2 ! 0 3 0 2 |LPM_ADD_SUB:85|addcore:adder|:71
- 2 - C 12 OR2 ! 0 2 0 4 |LPM_ADD_SUB:85|addcore:adder|:75
- 7 - C 12 DFFE + 0 2 0 2 cnt5 (:3)
- 2 - C 11 DFFE + 0 1 0 3 cnt4 (:4)
- 6 - C 12 DFFE + 0 2 0 1 cnt3 (:5)
- 4 - C 12 DFFE + 0 3 0 1 cnt2 (:6)
- 5 - C 12 DFFE + 0 2 0 2 cnt1 (:7)
- 2 - C 10 DFFE + 0 0 0 3 cnt0 (:8)
- 8 - C 12 DFFE + 0 3 1 0 clk (:9)
- 3 - C 12 OR2 ! 0 3 0 3 :35
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\travel\fdiv32.rpt
fdiv32
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/ 96( 3%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\travel\fdiv32.rpt
fdiv32
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clkin
Device-Specific Information: e:\travel\fdiv32.rpt
fdiv32
** EQUATIONS **
clkin : INPUT;
-- Node name is ':9' = 'clk'
-- Equation name is 'clk', location is LC8_C12, type is buried.
clk = DFFE( _EQ001, GLOBAL( clkin), VCC, VCC, VCC);
_EQ001 = clk & !cnt4
# clk & !_LC2_C12
# clk & cnt5
# !clk & cnt4 & !cnt5 & _LC2_C12;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = clk;
-- Node name is ':8' = 'cnt0'
-- Equation name is 'cnt0', location is LC2_C10, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL( clkin), VCC, VCC, VCC);
-- Node name is ':7' = 'cnt1'
-- Equation name is 'cnt1', location is LC5_C12, type is buried.
cnt1 = DFFE( _EQ002, GLOBAL( clkin), VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt1 & !_LC3_C12
# cnt0 & !cnt1 & !_LC3_C12;
-- Node name is ':6' = 'cnt2'
-- Equation name is 'cnt2', location is LC4_C12, type is buried.
cnt2 = DFFE( _EQ003, GLOBAL( clkin), VCC, VCC, VCC);
_EQ003 = !cnt1 & cnt2 & !_LC3_C12
# !cnt0 & cnt2 & !_LC3_C12
# cnt0 & cnt1 & !cnt2 & !_LC3_C12;
-- Node name is ':5' = 'cnt3'
-- Equation name is 'cnt3', location is LC6_C12, type is buried.
cnt3 = DFFE( _EQ004, GLOBAL( clkin), VCC, VCC, VCC);
_EQ004 = cnt3 & !_LC1_C12 & !_LC3_C12
# !cnt3 & _LC1_C12 & !_LC3_C12;
-- Node name is ':4' = 'cnt4'
-- Equation name is 'cnt4', location is LC2_C11, type is buried.
cnt4 = DFFE( _EQ005, GLOBAL( clkin), VCC, VCC, VCC);
_EQ005 = cnt4 & !_LC2_C12
# !cnt4 & _LC2_C12;
-- Node name is ':3' = 'cnt5'
-- Equation name is 'cnt5', location is LC7_C12, type is buried.
cnt5 = DFFE( _EQ006, GLOBAL( clkin), VCC, VCC, VCC);
_EQ006 = !cnt4 & cnt5
# cnt5 & !_LC2_C12;
-- Node name is '|LPM_ADD_SUB:85|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C12', type is buried
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ007);
_EQ007 = !cnt2
# !cnt1
# !cnt0;
-- Node name is '|LPM_ADD_SUB:85|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C12', type is buried
!_LC2_C12 = _LC2_C12~NOT;
_LC2_C12~NOT = LCELL( _EQ008);
_EQ008 = !cnt3
# !_LC1_C12;
-- Node name is ':35'
-- Equation name is '_LC3_C12', type is buried
!_LC3_C12 = _LC3_C12~NOT;
_LC3_C12~NOT = LCELL( _EQ009);
_EQ009 = cnt5
# !cnt4
# !_LC2_C12;
Project Information e:\travel\fdiv32.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,838K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -