fdiv32.fit

自己做的vhdl课程设计

-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 12/22/2002 13:19:04      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "fdiv32"
BEGIN

    DEVICE = "EP1K10TC100-3";

    "clkin"                        : INPUT_PIN  = 39     ;
    "clkout"                       : OUTPUT_PIN = 56     ;
    "|LPM_ADD_SUB:85|addcore:adder|:71" : LOCATION   = LC1_C12;
    "|LPM_ADD_SUB:85|addcore:adder|:75" : LOCATION   = LC2_C12;
    ":3"                           : LOCATION   = LC7_C12;  -- cnt5
    ":4"                           : LOCATION   = LC2_C11;  -- cnt4
    ":5"                           : LOCATION   = LC6_C12;  -- cnt3
    ":6"                           : LOCATION   = LC4_C12;  -- cnt2
    ":7"                           : LOCATION   = LC5_C12;  -- cnt1
    ":8"                           : LOCATION   = LC2_C10;  -- cnt0
    ":9"                           : LOCATION   = LC8_C12;  -- clk
    ":35"                          : LOCATION   = LC3_C12;

END;

INTERNAL_INFO "fdiv32"
BEGIN
	DEVICE = EP1K10TC100-3;
    OD5P39  : LORAX = "1:FB5->LC7_C12,->LC2_C11,->LC6_C12,->LC4_C12,->LC5_C12,->LC2_C10,->LC8_C12|";
    LC2_C12 : LORAX = "1:MSW2R2C10,G10R2,PA10R2C10->LC2_C11|";
    LC2_C11 : LORAX = "1:MSW1R2C10,G16R2,PA7R2C11->LC7_C12,->LC8_C12,->LC3_C12|";
    LC2_C10 : LORAX = "1:MSW1R2C9,G34R2,PA6R2C11->LC1_C12,->LC4_C12,->LC5_C12|";
    LC8_C12 : LORAX = "1:MSW4R2C10,HHL44R2->OH12R2P56|";
	LC1_C12 : LORAX2 = "X, LC4_C12, LC2_C10, LC5_C12";
	LC2_C12 : LORAX2 = "X, X, LC6_C12, LC1_C12";
	LC7_C12 : LORAX2 = "X, LC7_C12, LC2_C11, LC2_C12";
	LC2_C11 : LORAX2 = "X, X, LC2_C11, LC2_C12";
	LC6_C12 : LORAX2 = "X, LC6_C12, LC3_C12, LC1_C12";
	LC4_C12 : LORAX2 = "LC3_C12, LC4_C12, LC5_C12, LC2_C10";
	LC5_C12 : LORAX2 = "X, LC2_C10, LC5_C12, LC3_C12";
	LC2_C10 : LORAX2 = "X, X, X, LC2_C10";
	LC8_C12 : LORAX2 = "LC7_C12, LC2_C11, LC2_C12, LC8_C12";
	LC3_C12 : LORAX2 = "X, LC7_C12, LC2_C11, LC2_C12";
END;