📄 fuza.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 24 AND2 0 2 0 4 |LPM_ADD_SUB:336|addcore:adder|:59
- 5 - A 24 DFFE + 0 3 0 12 count3 (:22)
- 4 - A 24 DFFE + 0 2 0 13 count2 (:23)
- 3 - A 15 DFFE + 0 2 0 11 count1 (:24)
- 5 - A 15 DFFE + 0 1 0 10 count0 (:25)
- 4 - B 18 DFFE + 0 4 0 19 state2 (:26)
- 1 - B 18 DFFE + 0 2 0 14 state1 (:27)
- 5 - B 20 DFFE + 0 2 0 20 state0 (:28)
- 3 - A 24 OR2 ! 0 3 0 3 :379
- 7 - A 24 AND2 0 4 0 4 :406
- 1 - A 24 OR2 s 0 3 0 5 ~519~1
- 2 - B 18 OR2 0 3 0 3 :599
- 5 - B 18 OR2 s 0 4 0 2 ~626~1
- 7 - B 18 OR2 s 0 4 0 1 ~626~2
- 3 - B 18 OR2 s 0 4 0 2 ~632~1
- 6 - B 18 OR2 s 0 4 0 1 ~632~2
- 7 - B 20 OR2 s 0 4 0 1 ~636~1
- 8 - B 18 AND2 0 3 0 1 :783
- 3 - B 20 OR2 s 0 3 1 0 ~923~1
- 7 - B 21 OR2 s 0 3 1 0 ~923~2
- 6 - B 20 OR2 s 0 3 1 0 ~923~3
- 6 - B 21 OR2 0 3 1 0 :923
- 8 - B 20 OR2 s 0 3 1 0 ~983~1
- 1 - B 20 OR2 s 0 3 1 0 ~983~2
- 2 - B 20 OR2 s 0 3 1 0 ~983~3
- 4 - B 20 OR2 0 3 1 0 :983
- 8 - A 14 OR2 0 4 0 1 :1392
- 2 - A 14 OR2 0 3 1 0 :1416
- 7 - A 15 OR2 0 4 1 0 :1450
- 6 - A 15 OR2 0 4 1 0 :1486
- 1 - A 15 OR2 0 4 1 0 :1522
- 4 - A 14 OR2 ! 0 4 0 2 :1557
- 1 - A 14 OR2 0 2 1 0 :1558
- 5 - A 14 AND2 s 0 3 0 3 ~1594~1
- 6 - A 14 OR2 s 0 3 0 1 ~1594~2
- 3 - A 14 OR2 s 0 4 0 1 ~1594~3
- 2 - A 24 OR2 0 4 1 0 :1594
- 7 - A 14 OR2 ! 0 4 0 1 :1623
- 8 - A 24 OR2 0 4 1 0 :1630
- 4 - B 21 AND2 1 2 1 0 :1843
- 2 - B 21 OR2 1 3 1 0 :1916
- 1 - B 21 AND2 1 2 1 0 :1989
- 8 - B 21 OR2 1 3 1 0 :2062
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\fuza.rpt
fuza
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\fuza.rpt
fuza
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk1
Device-Specific Information: h:\jiaotongdeng\fuza.rpt
fuza
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: h:\jiaotongdeng\fuza.rpt
fuza
** EQUATIONS **
clk1 : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC5_A15, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ001 = !count0 & _LC1_A24;
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC3_A15, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ002 = !count0 & count1 & _LC1_A24
# count0 & !count1 & _LC1_A24;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC4_A24, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ003 = count2 & _LC1_A24 & !_LC6_A24
# !count2 & _LC1_A24 & _LC6_A24;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC5_A24, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ004 = !count2 & count3 & _LC1_A24
# count3 & _LC1_A24 & !_LC6_A24
# count2 & !count3 & _LC1_A24 & _LC6_A24;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC8_A24;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC2_A24;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC1_A14;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC1_A15;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC6_A15;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC7_A15;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC2_A14;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC6_B21;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC4_B20;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC4_B21;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC8_B20;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC3_B20;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC2_B21;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC7_B21;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC1_B20;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC1_B21;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC2_B20;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC6_B20;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC8_B21;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC5_B20, type is buried.
state0 = DFFE( _EQ005, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ005 = _LC7_B20
# _LC2_B18;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC1_B18, type is buried.
state1 = DFFE( _EQ006, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ006 = !_LC2_B18 & _LC6_B18;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC4_B18, type is buried.
state2 = DFFE( _EQ007, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC2_B18 & _LC7_B18
# !_LC2_B18 & _LC3_B18 & _LC8_B18;
-- Node name is '|LPM_ADD_SUB:336|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ008);
_EQ008 = count0 & count1;
-- Node name is ':379'
-- Equation name is '_LC3_A24', type is buried
!_LC3_A24 = _LC3_A24~NOT;
_LC3_A24~NOT = LCELL( _EQ009);
_EQ009 = count2 & count3
# count3 & _LC6_A24;
-- Node name is ':406'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ010);
_EQ010 = !count0 & count1 & !count2 & !count3;
-- Node name is '~519~1'
-- Equation name is '~519~1', location is LC1_A24, type is buried.
-- synthesized logic cell
_LC1_A24 = LCELL( _EQ011);
_EQ011 = !state0 & !state2
# _LC3_A24;
-- Node name is ':599'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ012);
_EQ012 = state1 & state2
# state0 & state2;
-- Node name is '~626~1'
-- Equation name is '~626~1', location is LC5_B18, type is buried.
-- synthesized logic cell
_LC5_B18 = LCELL( _EQ013);
_EQ013 = !_LC7_A24 & !state0 & !state2
# _LC3_A24 & state2
# _LC3_A24 & state0;
-- Node name is '~626~2'
-- Equation name is '~626~2', location is LC7_B18, type is buried.
-- synthesized logic cell
_LC7_B18 = LCELL( _EQ014);
_EQ014 = !state1 & state2
# !state0 & state2
# _LC5_B18 & state2;
-- Node name is '~632~1'
-- Equation name is '~632~1', location is LC3_B18, type is buried.
-- synthesized logic cell
_LC3_B18 = LCELL( _EQ015);
_EQ015 = _LC7_A24 & !state0 & !state2
# !_LC1_A24;
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