jiandan01.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

         # !count3
         #  count2;

-- Node name is ':382' 
-- Equation name is '_LC8_A3', type is buried 
!_LC8_A3 = _LC8_A3~NOT;
_LC8_A3~NOT = LCELL( _EQ010);
  _EQ010 = !state2
         # !state0 & !state1;

-- Node name is ':686' 
-- Equation name is '_LC4_A3', type is buried 
!_LC4_A3 = _LC4_A3~NOT;
_LC4_A3~NOT = LCELL( _EQ011);
  _EQ011 =  state0
         #  state2;

-- Node name is ':701' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ012);
  _EQ012 = !state0 & !state2;

-- Node name is ':716' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ013);
  _EQ013 =  state2
         # !state0 & !state1;

-- Node name is ':731' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ014);
  _EQ014 =  state2
         # !state0 & !state1;

-- Node name is '~793~1' 
-- Equation name is '~793~1', location is LC3_A1, type is buried.
-- synthesized logic cell 
_LC3_A1  = LCELL( _EQ015);
  _EQ015 =  state2
         #  state0 &  state1;

-- Node name is '~793~2' 
-- Equation name is '~793~2', location is LC1_A3, type is buried.
-- synthesized logic cell 
_LC1_A3  = LCELL( _EQ016);
  _EQ016 =  state2
         #  state0 &  state1;

-- Node name is '~793~3' 
-- Equation name is '~793~3', location is LC1_A1, type is buried.
-- synthesized logic cell 
_LC1_A1  = LCELL( _EQ017);
  _EQ017 =  state2
         #  state0 &  state1;

-- Node name is ':793' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ018);
  _EQ018 =  state2
         #  state0 &  state1;

-- Node name is '~853~1' 
-- Equation name is '~853~1', location is LC6_A1, type is buried.
-- synthesized logic cell 
_LC6_A1  = LCELL( _EQ019);
  _EQ019 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~853~2' 
-- Equation name is '~853~2', location is LC3_A3, type is buried.
-- synthesized logic cell 
_LC3_A3  = LCELL( _EQ020);
  _EQ020 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~853~3' 
-- Equation name is '~853~3', location is LC6_A3, type is buried.
-- synthesized logic cell 
_LC6_A3  = LCELL( _EQ021);
  _EQ021 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':853' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ022);
  _EQ022 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1257' 
-- Equation name is '_LC7_E3', type is buried 
_LC7_E3  = LCELL( _EQ023);
  _EQ023 = !count0 &  count1 & !count2 & !count3;

-- Node name is ':1269' 
-- Equation name is '_LC1_E1', type is buried 
!_LC1_E1 = _LC1_E1~NOT;
_LC1_E1~NOT = LCELL( _EQ024);
  _EQ024 =  count3
         #  count2
         #  count1
         # !count0;

-- Node name is ':1281' 
-- Equation name is '_LC3_E1', type is buried 
_LC3_E1  = LCELL( _EQ025);
  _EQ025 = !count0 & !count1 & !count2 & !count3;

-- Node name is ':1286' 
-- Equation name is '_LC8_E3', type is buried 
_LC8_E3  = LCELL( _EQ026);
  _EQ026 =  count3
         # !count0 &  count1
         #  count1 & !count2
         #  count0 & !count1 &  count2;

-- Node name is ':1320' 
-- Equation name is '_LC1_E3', type is buried 
_LC1_E3  = LCELL( _EQ027);
  _EQ027 =  count3
         # !count0 & !count1
         # !count1 &  count2
         # !count0 &  count2;

-- Node name is ':1350' 
-- Equation name is '_LC8_E1', type is buried 
_LC8_E1  = LCELL( _EQ028);
  _EQ028 =  count1 &  count3
         #  count2 &  count3
         # !count1 & !count2 & !count3
         # !count0 &  count3
         # !count0 & !count2
         # !count0 &  count1;

-- Node name is ':1356' 
-- Equation name is '_LC2_E1', type is buried 
_LC2_E1  = LCELL( _EQ029);
  _EQ029 = !_LC1_E1 &  _LC8_E1
         #  _LC3_E1;

-- Node name is ':1385' 
-- Equation name is '_LC7_E1', type is buried 
_LC7_E1  = LCELL( _EQ030);
  _EQ030 =  count2 &  count3
         #  count0 & !count2
         #  count0 &  count3
         # !count2 & !count3
         # !count1 &  count3
         # !count1 & !count2
         #  count0 & !count1
         # !count0 &  count1 &  count2
         # !count0 &  count1 & !count3;

-- Node name is ':1392' 
-- Equation name is '_LC4_E1', type is buried 
_LC4_E1  = LCELL( _EQ031);
  _EQ031 = !_LC1_E1 &  _LC7_E1
         # !_LC1_E1 &  _LC6_E5
         #  _LC3_E1;

-- Node name is '~1464~1' 
-- Equation name is '~1464~1', location is LC5_E1, type is buried.
-- synthesized logic cell 
_LC5_E1  = LCELL( _EQ032);
  _EQ032 = !count0 & !count1 &  count2 & !count3
         #  count0 &  count1 &  count2 & !count3
         # !count1 & !count2 &  count3
         # !count0 & !count2 &  count3;

-- Node name is ':1464' 
-- Equation name is '_LC6_E1', type is buried 
_LC6_E1  = LCELL( _EQ033);
  _EQ033 =  _LC1_E1
         #  _LC6_E5
         #  _LC5_E1
         #  _LC3_E1;

-- Node name is ':1493' 
-- Equation name is '_LC5_E3', type is buried 
_LC5_E3  = LCELL( _EQ034);
  _EQ034 =  count0 &  count2 & !count3
         #  count1 &  count2 & !count3
         # !count1 & !count2 &  count3
         # !count0 & !count2 &  count3;

-- Node name is '~1494~1' 
-- Equation name is '~1494~1', location is LC6_E5, type is buried.
-- synthesized logic cell 
_LC6_E5  = LCELL( _EQ035);
  _EQ035 =  _LC7_E3
         # !count2 & !count3 &  _LC7_E5;

-- Node name is ':1500' 
-- Equation name is '_LC4_E3', type is buried 
_LC4_E3  = LCELL( _EQ036);
  _EQ036 =  _LC3_E1
         # !_LC1_E1 &  _LC6_E5
         # !_LC1_E1 &  _LC5_E3;



Project Information                              h:\jiaotongdeng\jiandan01.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,475K