📄 jiandan01.rpt
字号:
73 - - - 01 OUTPUT 0 1 0 0 led1
78 - - F -- OUTPUT 0 1 0 0 led2
79 - - F -- OUTPUT 0 1 0 0 led3
80 - - F -- OUTPUT 0 1 0 0 led4
81 - - F -- OUTPUT 0 1 0 0 led5
82 - - E -- OUTPUT 0 1 0 0 led6
116 - - - 04 OUTPUT 0 1 0 0 pout1
114 - - - 04 OUTPUT 0 1 0 0 pout2
113 - - - 03 OUTPUT 0 1 0 0 pout3
112 - - - 02 OUTPUT 0 1 0 0 pout4
111 - - - 01 OUTPUT 0 1 0 0 pout5
110 - - - 01 OUTPUT 0 1 0 0 pout6
109 - - A -- OUTPUT 0 1 0 0 pout7
102 - - A -- OUTPUT 0 1 0 0 pout8
101 - - A -- OUTPUT 0 1 0 0 pout9
100 - - A -- OUTPUT 0 1 0 0 pout10
99 - - B -- OUTPUT 0 1 0 0 pout11
98 - - B -- OUTPUT 0 1 0 0 pout12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\jiaotongdeng\jiandan01.rpt
jiandan01
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - E 05 OR2 ! 0 2 0 4 |LPM_ADD_SUB:312|addcore:adder|:59
- 3 - E 05 DFFE + 1 3 0 11 count3 (:22)
- 5 - E 05 DFFE + 1 2 0 12 count2 (:23)
- 3 - E 03 DFFE + 1 2 0 10 count1 (:24)
- 2 - E 03 DFFE + 1 1 0 11 count0 (:25)
- 1 - E 05 DFFE + 1 3 0 13 state2 (:26)
- 4 - E 05 DFFE + 1 3 0 12 state1 (:27)
- 2 - E 05 DFFE + 1 2 0 15 state0 (:28)
- 8 - E 05 OR2 ! 0 3 0 3 :325
- 8 - A 03 OR2 ! 0 3 0 6 :382
- 4 - A 03 OR2 ! 0 2 1 0 :686
- 4 - A 01 AND2 0 2 1 0 :701
- 2 - A 01 OR2 0 3 1 0 :716
- 2 - A 03 OR2 0 3 1 0 :731
- 3 - A 01 OR2 s 0 3 1 0 ~793~1
- 1 - A 03 OR2 s 0 3 1 0 ~793~2
- 1 - A 01 OR2 s 0 3 1 0 ~793~3
- 5 - A 03 OR2 0 3 1 0 :793
- 6 - A 01 OR2 s 0 3 1 0 ~853~1
- 3 - A 03 OR2 s 0 3 1 0 ~853~2
- 6 - A 03 OR2 s 0 3 1 0 ~853~3
- 7 - A 03 OR2 0 3 1 0 :853
- 7 - E 03 AND2 0 4 1 1 :1257
- 1 - E 01 OR2 ! 0 4 0 4 :1269
- 3 - E 01 AND2 0 4 0 4 :1281
- 8 - E 03 OR2 0 4 1 0 :1286
- 1 - E 03 OR2 0 4 1 0 :1320
- 8 - E 01 OR2 0 4 0 1 :1350
- 2 - E 01 OR2 0 3 1 0 :1356
- 7 - E 01 OR2 0 4 0 1 :1385
- 4 - E 01 OR2 0 4 1 0 :1392
- 5 - E 01 OR2 s 0 4 0 1 ~1464~1
- 6 - E 01 OR2 0 4 1 0 :1464
- 5 - E 03 OR2 0 4 0 1 :1493
- 6 - E 05 OR2 s 0 4 0 3 ~1494~1
- 4 - E 03 OR2 0 4 1 0 :1500
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\jiandan01.rpt
jiandan01
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 2/ 96( 2%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 6/24( 25%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 6/24( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\jiandan01.rpt
jiandan01
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk1
Device-Specific Information: h:\jiaotongdeng\jiandan01.rpt
jiandan01
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: h:\jiaotongdeng\jiandan01.rpt
jiandan01
** EQUATIONS **
clk1 : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC2_E3, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk1), !reset, VCC, VCC);
_EQ001 = !count0 & !_LC8_A3;
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC3_E3, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk1), !reset, VCC, VCC);
_EQ002 = !count0 & count1 & !_LC8_A3
# count0 & !count1 & !_LC8_A3;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC5_E5, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk1), !reset, VCC, VCC);
_EQ003 = count2 & !_LC7_E5 & !_LC8_A3
# !count2 & _LC7_E5 & !_LC8_A3;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC3_E5, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk1), !reset, VCC, VCC);
_EQ004 = !count2 & count3 & !_LC8_A3
# count3 & !_LC7_E5 & !_LC8_A3
# count2 & !count3 & _LC7_E5 & !_LC8_A3;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC4_E3;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC6_E1;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = !_LC7_E3;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC4_E1;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC2_E1;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC1_E3;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC8_E3;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC5_A3;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC7_A3;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC4_A3;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC6_A1;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC3_A1;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC2_A1;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC1_A3;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC3_A3;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC4_A1;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC6_A3;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC1_A1;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC2_A3;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC2_E5, type is buried.
state0 = DFFE( _EQ005, GLOBAL( clk1), !reset, VCC, VCC);
_EQ005 = _LC8_E5 & !state0
# !_LC8_E5 & state0
# _LC8_A3;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC4_E5, type is buried.
state1 = DFFE( _EQ006, GLOBAL( clk1), !reset, VCC, VCC);
_EQ006 = !_LC8_A3 & _LC8_E5 & state0 & !state1
# !_LC8_A3 & !state0 & state1
# !_LC8_A3 & !_LC8_E5 & state1;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC1_E5, type is buried.
state2 = DFFE( _EQ007, GLOBAL( clk1), !reset, VCC, VCC);
_EQ007 = _LC8_E5 & state0 & state1 & !state2
# !state0 & !state1 & state2;
-- Node name is '|LPM_ADD_SUB:312|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E5', type is buried
!_LC7_E5 = _LC7_E5~NOT;
_LC7_E5~NOT = LCELL( _EQ008);
_EQ008 = !count1
# !count0;
-- Node name is ':325'
-- Equation name is '_LC8_E5', type is buried
!_LC8_E5 = _LC8_E5~NOT;
_LC8_E5~NOT = LCELL( _EQ009);
_EQ009 = !_LC7_E5
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -