fuza05.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

         #  cn13
         #  _LC1_B16;

-- Node name is ':694' 
-- Equation name is '_LC1_B4', type is buried 
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ021);
  _EQ021 = !state2
         #  state1
         #  state0;

-- Node name is '~1119~1' 
-- Equation name is '~1119~1', location is LC2_B10, type is buried.
-- synthesized logic cell 
_LC2_B10 = LCELL(!_LC6_B17);

-- Node name is '~1137~1' 
-- Equation name is '~1137~1', location is LC7_B20, type is buried.
-- synthesized logic cell 
_LC7_B20 = LCELL( _EQ022);
  _EQ022 = !cn10 &  _LC1_B17
         #  cn10 & !_LC1_B17;

-- Node name is '~1560~1' 
-- Equation name is '~1560~1', location is LC5_B10, type is buried.
-- synthesized logic cell 
_LC5_B10 = LCELL( _EQ023);
  _EQ023 =  state2
         #  state0 &  state1;

-- Node name is '~1560~2' 
-- Equation name is '~1560~2', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ024);
  _EQ024 =  state2
         #  state0 &  state1;

-- Node name is '~1560~3' 
-- Equation name is '~1560~3', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ025);
  _EQ025 =  state2
         #  state0 &  state1;

-- Node name is ':1560' 
-- Equation name is '_LC7_B10', type is buried 
_LC7_B10 = LCELL( _EQ026);
  _EQ026 =  state2
         #  state0 &  state1;

-- Node name is '~1620~1' 
-- Equation name is '~1620~1', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ027);
  _EQ027 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~1620~2' 
-- Equation name is '~1620~2', location is LC4_B4, type is buried.
-- synthesized logic cell 
_LC4_B4  = LCELL( _EQ028);
  _EQ028 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~1620~3' 
-- Equation name is '~1620~3', location is LC6_B4, type is buried.
-- synthesized logic cell 
_LC6_B4  = LCELL( _EQ029);
  _EQ029 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1620' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ030);
  _EQ030 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1722' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ031);
  _EQ031 =  cn03 & !count
         #  cn13 &  count;

-- Node name is ':1728' 
-- Equation name is '_LC3_B16', type is buried 
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ032);
  _EQ032 = !cn02 & !count
         # !cn12 &  count
         # !cn02 & !cn12;

-- Node name is ':1734' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ033);
  _EQ033 =  cn01 & !count
         #  cn11 &  count;

-- Node name is ':1740' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ034);
  _EQ034 =  cn00 & !count
         #  cn10 &  count;

-- Node name is ':1751' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = LCELL( _EQ035);
  _EQ035 = !_LC3_B16 & !_LC3_B17 & !_LC4_B16 & !_LC4_B20;

-- Node name is ':1756' 
-- Equation name is '_LC4_B24', type is buried 
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = LCELL( _EQ036);
  _EQ036 =  _LC3_B17
         # !_LC4_B20
         #  _LC4_B16
         #  _LC3_B16;

-- Node name is '~1761~1' 
-- Equation name is '~1761~1', location is LC3_B13, type is buried.
-- synthesized logic cell 
_LC3_B13 = LCELL( _EQ037);
  _EQ037 =  _LC3_B17
         #  _LC4_B20;

-- Node name is ':1761' 
-- Equation name is '_LC6_B24', type is buried 
!_LC6_B24 = _LC6_B24~NOT;
_LC6_B24~NOT = LCELL( _EQ038);
  _EQ038 =  _LC3_B17
         #  _LC4_B20
         #  _LC3_B16
         # !_LC4_B16;

-- Node name is '~1776~1' 
-- Equation name is '~1776~1', location is LC5_B24, type is buried.
-- synthesized logic cell 
_LC5_B24 = LCELL( _EQ039);
  _EQ039 =  _LC3_B17
         # !_LC4_B20
         #  _LC4_B16;

-- Node name is ':1844' 
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = LCELL( _EQ040);
  _EQ040 =  _LC3_B17
         # !_LC3_B16 &  _LC4_B16
         #  _LC3_B16 & !_LC4_B16
         #  _LC4_B16 & !_LC4_B20
         #  _LC3_B16 & !_LC4_B20;

-- Node name is ':1869' 
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ041);
  _EQ041 =  _LC3_B17
         #  _LC3_B16 & !_LC4_B16
         #  _LC3_B16 & !_LC4_B20
         # !_LC4_B16 & !_LC4_B20;

-- Node name is ':1896' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ042);
  _EQ042 =  _LC3_B17
         #  _LC4_B16 & !_LC4_B20
         # !_LC3_B16 & !_LC4_B20;

-- Node name is ':1916' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = LCELL( _EQ043);
  _EQ043 =  _LC3_B17
         # !_LC3_B16
         # !_LC4_B16 &  _LC4_B20
         #  _LC4_B16 & !_LC4_B20;

-- Node name is ':1923' 
-- Equation name is '_LC6_B13', type is buried 
_LC6_B13 = LCELL( _EQ044);
  _EQ044 = !_LC4_B24 &  _LC8_B24
         # !_LC4_B24 &  _LC5_B13
         #  _LC1_B24;

-- Node name is '~1977~1' 
-- Equation name is '~1977~1', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ045);
  _EQ045 = !_LC3_B16 & !_LC3_B17 &  _LC4_B16;

-- Node name is '~1977~2' 
-- Equation name is '~1977~2', location is LC8_B16, type is buried.
-- synthesized logic cell 
_LC8_B16 = LCELL( _EQ046);
  _EQ046 =  cn13 &  count
         # !cn11 &  count
         #  cn10 &  count;

-- Node name is '~1977~3' 
-- Equation name is '~1977~3', location is LC2_B17, type is buried.
-- synthesized logic cell 
_LC2_B17 = LCELL( _EQ047);
  _EQ047 =  cn03 & !count
         # !cn01 & !count
         #  cn00 & !count;

-- Node name is '~1977~4' 
-- Equation name is '~1977~4', location is LC2_B16, type is buried.
-- synthesized logic cell 
_LC2_B16 = LCELL( _EQ048);
  _EQ048 = !_LC3_B16
         #  _LC5_B24 &  _LC8_B16
         #  _LC2_B17 &  _LC5_B24;

-- Node name is ':1977' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = LCELL( _EQ049);
  _EQ049 =  _LC5_B13
         #  _LC2_B16
         #  _LC1_B24
         # !_LC4_B13;

-- Node name is ':2004' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = LCELL( _EQ050);
  _EQ050 =  _LC1_B24
         #  _LC4_B13;

-- Node name is ':2006' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ051);
  _EQ051 = !_LC3_B16 & !_LC4_B24
         #  _LC4_B16 & !_LC4_B24
         #  _LC3_B13 & !_LC4_B24;

-- Node name is ':2203' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ052);
  _EQ052 =  clk1 & !state0 & !state2;

-- Node name is ':2276' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ053);
  _EQ053 =  clk1 &  state2
         #  clk1 & !state0 & !state1;

-- Node name is ':2349' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ054);
  _EQ054 =  clk1 & !state0 & !state2;

-- Node name is ':2422' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ055);
  _EQ055 =  clk1 &  state2
         #  clk1 & !state0 & !state1;



Project Information                                 h:\jiaotongdeng\fuza05.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,477K