📄 fuza05.rpt
字号:
- 5 - B 04 OR2 s 0 3 1 0 ~1560~3
- 7 - B 10 OR2 0 3 1 0 :1560
- 3 - B 04 OR2 s 0 3 1 0 ~1620~1
- 4 - B 04 OR2 s 0 3 1 0 ~1620~2
- 6 - B 04 OR2 s 0 3 1 0 ~1620~3
- 6 - B 10 OR2 0 3 1 0 :1620
- 3 - B 17 OR2 0 3 0 10 :1722
- 3 - B 16 OR2 ! 0 3 0 10 :1728
- 4 - B 16 OR2 0 3 0 10 :1734
- 4 - B 20 OR2 0 3 0 9 :1740
- 1 - B 24 AND2 0 4 0 3 :1751
- 4 - B 24 OR2 ! 0 4 0 2 :1756
- 3 - B 13 OR2 s 0 2 0 1 ~1761~1
- 6 - B 24 OR2 ! 0 4 1 0 :1761
- 5 - B 24 OR2 s 0 3 0 1 ~1776~1
- 7 - B 24 OR2 0 4 1 0 :1844
- 3 - B 24 OR2 0 4 1 0 :1869
- 2 - B 24 OR2 0 4 1 0 :1896
- 8 - B 24 OR2 0 4 0 1 :1916
- 6 - B 13 OR2 0 4 1 0 :1923
- 5 - B 13 AND2 s 0 3 0 2 ~1977~1
- 8 - B 16 OR2 s 0 4 0 1 ~1977~2
- 2 - B 17 OR2 s 0 4 0 1 ~1977~3
- 2 - B 16 OR2 s 0 4 0 1 ~1977~4
- 2 - B 13 OR2 0 4 1 0 :1977
- 1 - B 13 OR2 0 2 1 0 :2004
- 4 - B 13 OR2 0 4 0 2 :2006
- 1 - B 02 AND2 1 2 1 0 :2203
- 7 - B 04 OR2 1 3 1 0 :2276
- 2 - B 02 AND2 1 2 1 0 :2349
- 8 - B 04 OR2 1 3 1 0 :2422
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\fuza05.rpt
fuza05
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 10/ 96( 10%) 7/ 48( 14%) 18/ 48( 37%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\fuza05.rpt
fuza05
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 15 clk1
INPUT 1 clk2
Device-Specific Information: h:\jiaotongdeng\fuza05.rpt
fuza05
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 reset
Device-Specific Information: h:\jiaotongdeng\fuza05.rpt
fuza05
** EQUATIONS **
clk1 : INPUT;
clk2 : INPUT;
reset : INPUT;
-- Node name is ':27' = 'cn00'
-- Equation name is 'cn00', location is LC5_B20, type is buried.
cn00 = DFFE( _EQ001, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ001 = !cn00 & !_LC6_B17
# !cn00 & _LC1_B4
# !cn00 & !_LC2_B4;
-- Node name is ':26' = 'cn01'
-- Equation name is 'cn01', location is LC2_B20, type is buried.
!cn01 = cn01~NOT;
cn01~NOT = DFFE( _EQ002, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ002 = !_LC6_B17 & !_LC6_B20
# _LC1_B4 & !_LC6_B20
# _LC1_B4 & _LC6_B17
# !_LC2_B4 & !_LC6_B20
# !_LC2_B4 & _LC6_B17;
-- Node name is ':25' = 'cn02'
-- Equation name is 'cn02', location is LC3_B20, type is buried.
cn02 = DFFE( _EQ003, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC6_B17 & _LC8_B20;
-- Node name is ':24' = 'cn03'
-- Equation name is 'cn03', location is LC8_B17, type is buried.
cn03 = DFFE( _EQ004, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ004 = _LC1_B4 & _LC7_B17
# _LC1_B4 & _LC6_B17
# !_LC6_B17 & _LC7_B17
# !_LC2_B4 & _LC7_B17
# !_LC2_B4 & _LC6_B17;
-- Node name is ':31' = 'cn10'
-- Equation name is 'cn10', location is LC1_B20, type is buried.
cn10 = DFFE( _EQ005, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC6_B17 & _LC7_B20
# !_LC2_B4 & _LC7_B20
# _LC1_B4 & _LC7_B20
# !_LC2_B4 & _LC6_B17
# _LC1_B4 & _LC6_B17;
-- Node name is ':30' = 'cn11'
-- Equation name is 'cn11', location is LC5_B16, type is buried.
cn11 = DFFE( _EQ006, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ006 = cn10 & cn11 & _LC2_B10
# cn11 & !_LC1_B17 & _LC2_B10
# !cn10 & !cn11 & _LC1_B17 & _LC2_B10;
-- Node name is ':29' = 'cn12'
-- Equation name is 'cn12', location is LC7_B16, type is buried.
cn12 = DFFE( _EQ007, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ007 = cn12 & _LC2_B10 & _LC6_B16
# cn12 & !_LC1_B17 & _LC2_B10
# !cn12 & _LC1_B17 & _LC2_B10 & !_LC6_B16;
-- Node name is ':28' = 'cn13'
-- Equation name is 'cn13', location is LC4_B17, type is buried.
cn13 = DFFE( _EQ008, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ008 = cn13 & !_LC1_B17 & _LC2_B10
# cn13 & _LC1_B16 & _LC2_B10
# !cn13 & !_LC1_B16 & _LC1_B17 & _LC2_B10;
-- Node name is ':47' = 'count'
-- Equation name is 'count', location is LC4_C22, type is buried.
count = DFFE(!count, GLOBAL( clk2), VCC, VCC, VCC);
-- Node name is 'led7s0'
-- Equation name is 'led7s0', type is output
led7s0 = _LC1_B13;
-- Node name is 'led7s1'
-- Equation name is 'led7s1', type is output
led7s1 = _LC2_B13;
-- Node name is 'led7s2'
-- Equation name is 'led7s2', type is output
led7s2 = !_LC6_B24;
-- Node name is 'led7s3'
-- Equation name is 'led7s3', type is output
led7s3 = _LC6_B13;
-- Node name is 'led7s4'
-- Equation name is 'led7s4', type is output
led7s4 = _LC2_B24;
-- Node name is 'led7s5'
-- Equation name is 'led7s5', type is output
led7s5 = _LC3_B24;
-- Node name is 'led7s6'
-- Equation name is 'led7s6', type is output
led7s6 = _LC7_B24;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC7_B10;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC6_B10;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC1_B2;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC3_B4;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC5_B10;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC7_B4;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC8_B10;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC4_B4;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC2_B2;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC6_B4;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC5_B4;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC8_B4;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = count;
-- Node name is ':34' = 'state0'
-- Equation name is 'state0', location is LC1_B10, type is buried.
state0 = DFFE( _EQ009, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ009 = state1 & state2
# state0 & state2
# _LC6_B17 & !state0
# !_LC6_B17 & state0;
-- Node name is ':33' = 'state1'
-- Equation name is 'state1', location is LC4_B10, type is buried.
state1 = DFFE( _EQ010, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ010 = !state0 & state1 & !state2
# !_LC6_B17 & state1 & !state2
# _LC6_B17 & state0 & !state1 & !state2;
-- Node name is ':32' = 'state2'
-- Equation name is 'state2', location is LC3_B10, type is buried.
state2 = DFFE( _EQ011, GLOBAL( clk1), GLOBAL(!reset), VCC, VCC);
_EQ011 = _LC6_B17 & state0 & state1 & !state2
# !_LC6_B17 & !state0 & !state1 & state2;
-- Node name is '|LPM_ADD_SUB:419|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B16', type is buried
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ012);
_EQ012 = !cn10 & !cn11;
-- Node name is '|LPM_ADD_SUB:419|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ013);
_EQ013 = cn12
# cn10
# cn11;
-- Node name is '|LPM_ADD_SUB:453|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B17', type is buried
!_LC5_B17 = _LC5_B17~NOT;
_LC5_B17~NOT = LCELL( _EQ014);
_EQ014 = !cn00 & !cn01 & !cn02;
-- Node name is ':397'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ015);
_EQ015 = !cn03 & cn13 & !_LC5_B17
# !cn03 & _LC1_B16 & !_LC5_B17;
-- Node name is ':475'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = LCELL( _EQ016);
_EQ016 = cn03 & _LC5_B17
# !cn03 & !_LC5_B17
# _LC1_B17;
-- Node name is ':483'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = LCELL( _EQ017);
_EQ017 = cn00 & cn02 & !_LC1_B17
# cn01 & cn02 & !_LC1_B17
# !cn00 & !cn01 & !cn02 & !_LC1_B17;
-- Node name is ':489'
-- Equation name is '_LC6_B20', type is buried
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = LCELL( _EQ018);
_EQ018 = cn00 & !cn01
# !cn00 & cn01
# _LC1_B17;
-- Node name is '~534~1'
-- Equation name is '~534~1', location is LC2_B4, type is buried.
-- synthesized logic cell
_LC2_B4 = LCELL( _EQ019);
_EQ019 = state2
# state0;
-- Node name is ':564'
-- Equation name is '_LC6_B17', type is buried
!_LC6_B17 = _LC6_B17~NOT;
_LC6_B17~NOT = LCELL( _EQ020);
_EQ020 = cn03
# _LC5_B17
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