jiandan.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

pout6    =  _LC3_A1;

-- Node name is 'pout7' 
-- Equation name is 'pout7', type is output 
pout7    =  _LC1_A4;

-- Node name is 'pout8' 
-- Equation name is 'pout8', type is output 
pout8    =  _LC3_A4;

-- Node name is 'pout9' 
-- Equation name is 'pout9', type is output 
pout9    =  _LC4_A1;

-- Node name is 'pout10' 
-- Equation name is 'pout10', type is output 
pout10   =  _LC5_A4;

-- Node name is 'pout11' 
-- Equation name is 'pout11', type is output 
pout11   =  _LC1_A1;

-- Node name is 'pout12' 
-- Equation name is 'pout12', type is output 
pout12   =  _LC2_A4;

-- Node name is ':21' = 'state0' 
-- Equation name is 'state0', location is LC7_A4, type is buried.
state0   = DFFE( _EQ005, GLOBAL( clk1), !reset,  VCC,  VCC);
  _EQ005 = !_LC2_A8 &  state0 & !state2
         #  _LC2_A8 & !state0 & !state2
         #  _LC2_A8 & !state0 & !state1;

-- Node name is ':20' = 'state1' 
-- Equation name is 'state1', location is LC1_A8, type is buried.
state1   = DFFE( _EQ006, GLOBAL( clk1), !reset,  VCC,  VCC);
  _EQ006 = !_LC2_A8 &  state1 & !state2
         # !state0 &  state1 & !state2
         #  _LC2_A8 &  state0 & !state1 & !state2;

-- Node name is ':19' = 'state2' 
-- Equation name is 'state2', location is LC4_A4, type is buried.
state2   = DFFE( _EQ007, GLOBAL( clk1), !reset,  VCC,  VCC);
  _EQ007 =  _LC2_A8 &  state0 &  state1 & !state2
         # !state0 & !state1 &  state2;

-- Node name is '|LPM_ADD_SUB:305|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A8', type is buried 
_LC4_A8  = LCELL( _EQ008);
  _EQ008 =  count0 &  count1;

-- Node name is ':318' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = LCELL( _EQ009);
  _EQ009 =  count0 &  count1 & !count2 &  count3;

-- Node name is ':375' 
-- Equation name is '_LC3_A8', type is buried 
!_LC3_A8 = _LC3_A8~NOT;
_LC3_A8~NOT = LCELL( _EQ010);
  _EQ010 = !state2
         # !state0 & !state1;

-- Node name is ':679' 
-- Equation name is '_LC2_A3', type is buried 
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ011);
  _EQ011 =  state0
         #  state2;

-- Node name is ':694' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ012);
  _EQ012 = !state0 & !state2;

-- Node name is ':709' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ013);
  _EQ013 =  state2
         # !state0 & !state1;

-- Node name is ':724' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ014);
  _EQ014 =  state2
         # !state0 & !state1;

-- Node name is '~786~1' 
-- Equation name is '~786~1', location is LC2_A1, type is buried.
-- synthesized logic cell 
_LC2_A1  = LCELL( _EQ015);
  _EQ015 =  state2
         #  state0 &  state1;

-- Node name is '~786~2' 
-- Equation name is '~786~2', location is LC1_A4, type is buried.
-- synthesized logic cell 
_LC1_A4  = LCELL( _EQ016);
  _EQ016 =  state2
         #  state0 &  state1;

-- Node name is '~786~3' 
-- Equation name is '~786~3', location is LC1_A1, type is buried.
-- synthesized logic cell 
_LC1_A1  = LCELL( _EQ017);
  _EQ017 =  state2
         #  state0 &  state1;

-- Node name is ':786' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = LCELL( _EQ018);
  _EQ018 =  state2
         #  state0 &  state1;

-- Node name is '~846~1' 
-- Equation name is '~846~1', location is LC6_A1, type is buried.
-- synthesized logic cell 
_LC6_A1  = LCELL( _EQ019);
  _EQ019 = !state0 &  state1 & !state2
         #  state0 & !state1 & !state2;

-- Node name is '~846~2' 
-- Equation name is '~846~2', location is LC3_A4, type is buried.
-- synthesized logic cell 
_LC3_A4  = LCELL( _EQ020);
  _EQ020 = !state0 &  state1 & !state2
         #  state0 & !state1 & !state2;

-- Node name is '~846~3' 
-- Equation name is '~846~3', location is LC5_A4, type is buried.
-- synthesized logic cell 
_LC5_A4  = LCELL( _EQ021);
  _EQ021 = !state0 &  state1 & !state2
         #  state0 & !state1 & !state2;

-- Node name is ':846' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = LCELL( _EQ022);
  _EQ022 = !state0 &  state1 & !state2
         #  state0 & !state1 & !state2;



Project Information                                h:\jiaotongdeng\jiandan.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,103K