📄 jiandan.rpt
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Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 5 0 1 8 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 5 0 1 8 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22/0
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk1
31 - - F -- INPUT 0 0 0 7 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
116 - - - 04 OUTPUT 0 1 0 0 pout1
114 - - - 04 OUTPUT 0 1 0 0 pout2
113 - - - 03 OUTPUT 0 1 0 0 pout3
112 - - - 02 OUTPUT 0 1 0 0 pout4
111 - - - 01 OUTPUT 0 1 0 0 pout5
110 - - - 01 OUTPUT 0 1 0 0 pout6
109 - - A -- OUTPUT 0 1 0 0 pout7
102 - - A -- OUTPUT 0 1 0 0 pout8
101 - - A -- OUTPUT 0 1 0 0 pout9
100 - - A -- OUTPUT 0 1 0 0 pout10
99 - - B -- OUTPUT 0 1 0 0 pout11
98 - - B -- OUTPUT 0 1 0 0 pout12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 08 AND2 0 2 0 1 |LPM_ADD_SUB:305|addcore:adder|:59
- 5 - A 08 DFFE + 1 3 0 1 count3 (:15)
- 6 - A 08 DFFE + 1 3 0 2 count2 (:16)
- 7 - A 08 DFFE + 1 2 0 3 count1 (:17)
- 8 - A 08 DFFE + 1 3 0 4 count0 (:18)
- 4 - A 04 DFFE + 1 3 0 16 state2 (:19)
- 1 - A 08 DFFE + 1 3 0 14 state1 (:20)
- 7 - A 04 DFFE + 1 3 0 16 state0 (:21)
- 2 - A 08 AND2 0 4 0 3 :318
- 3 - A 08 OR2 ! 0 3 0 3 :375
- 2 - A 03 OR2 ! 0 2 1 0 :679
- 4 - A 01 AND2 0 2 1 0 :694
- 3 - A 01 OR2 0 3 1 0 :709
- 2 - A 04 OR2 0 3 1 0 :724
- 2 - A 01 OR2 s 0 3 1 0 ~786~1
- 1 - A 04 OR2 s 0 3 1 0 ~786~2
- 1 - A 01 OR2 s 0 3 1 0 ~786~3
- 6 - A 04 OR2 0 3 1 0 :786
- 6 - A 01 OR2 s 0 3 1 0 ~846~1
- 3 - A 04 OR2 s 0 3 1 0 ~846~2
- 5 - A 04 OR2 s 0 3 1 0 ~846~3
- 8 - A 04 OR2 0 3 1 0 :846
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk1
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: h:\jiaotongdeng\jiandan.rpt
jiandan
** EQUATIONS **
clk1 : INPUT;
reset : INPUT;
-- Node name is ':18' = 'count0'
-- Equation name is 'count0', location is LC8_A8, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk1), !reset, VCC, VCC);
_EQ001 = !count0 & !state2
# !count0 & !state0 & !state1;
-- Node name is ':17' = 'count1'
-- Equation name is 'count1', location is LC7_A8, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk1), !reset, VCC, VCC);
_EQ002 = count0 & !count1 & !_LC3_A8
# !count0 & count1 & !_LC3_A8;
-- Node name is ':16' = 'count2'
-- Equation name is 'count2', location is LC6_A8, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk1), !reset, VCC, VCC);
_EQ003 = !count0 & count2 & !_LC3_A8
# !count1 & count2 & !_LC3_A8
# count0 & count1 & !count2 & !_LC3_A8;
-- Node name is ':15' = 'count3'
-- Equation name is 'count3', location is LC5_A8, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk1), !reset, VCC, VCC);
_EQ004 = !count2 & count3 & !_LC3_A8
# count3 & !_LC3_A8 & !_LC4_A8
# count2 & !count3 & !_LC3_A8 & _LC4_A8;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC6_A4;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC8_A4;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC2_A3;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC6_A1;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC2_A1;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
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