jtd1.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

  _EQ008 =  state0
         #  state2;

-- Node name is ':698' 
-- Equation name is '_LC7_C6', type is buried 
_LC7_C6  = LCELL( _EQ009);
  _EQ009 = !state0 & !state2;

-- Node name is ':713' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ010);
  _EQ010 =  state2
         # !state0 & !state1;

-- Node name is ':728' 
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ011);
  _EQ011 =  state2
         # !state0 & !state1;

-- Node name is '~790~1' 
-- Equation name is '~790~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
_LC1_C5  = LCELL( _EQ012);
  _EQ012 =  state2
         #  state0 &  state1;

-- Node name is '~790~2' 
-- Equation name is '~790~2', location is LC8_C5, type is buried.
-- synthesized logic cell 
_LC8_C5  = LCELL( _EQ013);
  _EQ013 =  state2
         #  state0 &  state1;

-- Node name is '~790~3' 
-- Equation name is '~790~3', location is LC4_C5, type is buried.
-- synthesized logic cell 
_LC4_C5  = LCELL( _EQ014);
  _EQ014 =  state2
         #  state0 &  state1;

-- Node name is ':790' 
-- Equation name is '_LC3_C6', type is buried 
_LC3_C6  = LCELL( _EQ015);
  _EQ015 =  state2
         #  state0 &  state1;

-- Node name is '~850~1' 
-- Equation name is '~850~1', location is LC7_C5, type is buried.
-- synthesized logic cell 
_LC7_C5  = LCELL( _EQ016);
  _EQ016 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~850~2' 
-- Equation name is '~850~2', location is LC2_C5, type is buried.
-- synthesized logic cell 
_LC2_C5  = LCELL( _EQ017);
  _EQ017 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~850~3' 
-- Equation name is '~850~3', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ018);
  _EQ018 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':850' 
-- Equation name is '_LC8_C6', type is buried 
_LC8_C6  = LCELL( _EQ019);
  _EQ019 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1128' 
-- Equation name is '_LC5_C21', type is buried 
!_LC5_C21 = _LC5_C21~NOT;
_LC5_C21~NOT = LCELL( _EQ020);
  _EQ020 =  count2
         #  count0
         # !count1
         #  count3;

-- Node name is ':1140' 
-- Equation name is '_LC4_C21', type is buried 
!_LC4_C21 = _LC4_C21~NOT;
_LC4_C21~NOT = LCELL( _EQ021);
  _EQ021 =  count3
         #  count2
         #  count1
         # !count0;

-- Node name is ':1152' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ022);
  _EQ022 = !count0 & !count1 & !count2 & !count3;

-- Node name is ':1157' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ023);
  _EQ023 = !count1 &  count2
         #  count1 & !count2
         #  count3
         # !count0 &  count2
         # !count0 &  count1;

-- Node name is ':1191' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ024);
  _EQ024 =  count3
         # !count0 & !count1
         # !count1 &  count2
         # !count0 &  count2;

-- Node name is ':1221' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = LCELL( _EQ025);
  _EQ025 =  count1 &  count3
         #  count2 &  count3
         # !count1 & !count2 & !count3
         # !count0 &  count3
         # !count0 & !count2
         # !count0 &  count1;

-- Node name is ':1227' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = LCELL( _EQ026);
  _EQ026 = !_LC4_C21 &  _LC8_C21
         #  _LC1_C15;

-- Node name is ':1256' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ027);
  _EQ027 =  count2 &  count3
         #  count0 & !count2
         #  count0 &  count3
         # !count2 & !count3
         # !count1 &  count3
         # !count1 & !count2
         #  count0 & !count1
         # !count0 &  count1 &  count2
         # !count0 &  count1 & !count3;

-- Node name is ':1263' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ028);
  _EQ028 = !_LC4_C21 &  _LC8_C15
         # !_LC4_C21 &  _LC5_C15
         #  _LC1_C15;

-- Node name is '~1335~1' 
-- Equation name is '~1335~1', location is LC7_C15, type is buried.
-- synthesized logic cell 
_LC7_C15 = LCELL( _EQ029);
  _EQ029 = !count0 & !count1 &  count2 & !count3
         #  count0 &  count1 &  count2 & !count3
         # !count1 & !count2 &  count3
         # !count0 & !count2 &  count3;

-- Node name is ':1335' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ030);
  _EQ030 =  _LC4_C21
         #  _LC5_C15
         #  _LC7_C15
         #  _LC1_C15;

-- Node name is ':1364' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ031);
  _EQ031 =  count0 &  count2 & !count3
         #  count1 &  count2 & !count3
         # !count1 & !count2 &  count3
         # !count0 & !count2 &  count3;

-- Node name is '~1365~1' 
-- Equation name is '~1365~1', location is LC5_C15, type is buried.
-- synthesized logic cell 
_LC5_C15 = LCELL( _EQ032);
  _EQ032 =  count1 & !count2 & !count3;

-- Node name is ':1371' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ033);
  _EQ033 =  _LC1_C15
         # !_LC4_C21 &  _LC5_C15
         # !_LC4_C21 &  _LC6_C15;



Project Information                               e:\eda\jiaotongdeng\jtd1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,681K