📄 jtd1.rpt
字号:
89 - - C -- OUTPUT 0 1 0 0 pout7
98 - - B -- OUTPUT 0 1 0 0 pout8
118 - - - 06 OUTPUT 0 1 0 0 pout9
70 - - - 05 OUTPUT 0 1 0 0 pout10
92 - - C -- OUTPUT 0 1 0 0 pout11
33 - - F -- OUTPUT 0 1 0 0 pout12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\jiaotongdeng\jtd1.rpt
jtd1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 21 DFFE + 0 3 0 11 count3 (:22)
- 1 - C 21 DFFE + 0 2 0 12 count2 (:23)
- 1 - C 24 DFFE + 0 1 0 13 count1 (:24)
- 2 - C 24 DFFE + 0 0 0 13 count0 (:25)
- 3 - C 24 DFFE + 0 3 0 14 state2 (:26)
- 5 - C 24 DFFE + 0 3 0 12 state1 (:27)
- 4 - C 24 DFFE + 0 3 0 14 state0 (:28)
- 6 - C 24 OR2 ! 0 4 0 3 :405
- 5 - C 06 OR2 ! 0 2 1 0 :683
- 7 - C 06 AND2 0 2 1 0 :698
- 5 - C 05 OR2 0 3 1 0 :713
- 6 - C 05 OR2 0 3 1 0 :728
- 1 - C 05 OR2 s 0 3 1 0 ~790~1
- 8 - C 05 OR2 s 0 3 1 0 ~790~2
- 4 - C 05 OR2 s 0 3 1 0 ~790~3
- 3 - C 06 OR2 0 3 1 0 :790
- 7 - C 05 OR2 s 0 3 1 0 ~850~1
- 2 - C 05 OR2 s 0 3 1 0 ~850~2
- 3 - C 05 OR2 s 0 3 1 0 ~850~3
- 8 - C 06 OR2 0 3 1 0 :850
- 5 - C 21 OR2 ! 0 4 1 0 :1128
- 4 - C 21 OR2 ! 0 4 0 4 :1140
- 1 - C 15 AND2 0 4 0 4 :1152
- 6 - C 21 OR2 0 4 1 0 :1157
- 3 - C 21 OR2 0 4 1 0 :1191
- 8 - C 21 OR2 0 4 0 1 :1221
- 7 - C 21 OR2 0 3 1 0 :1227
- 8 - C 15 OR2 0 4 0 1 :1256
- 3 - C 15 OR2 0 4 1 0 :1263
- 7 - C 15 OR2 s 0 4 0 1 ~1335~1
- 4 - C 15 OR2 0 4 1 0 :1335
- 6 - C 15 OR2 0 4 0 1 :1364
- 5 - C 15 AND2 s 0 3 0 3 ~1365~1
- 2 - C 15 OR2 0 4 1 0 :1371
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\jiaotongdeng\jtd1.rpt
jtd1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 8/ 96( 8%) 3/ 48( 6%) 6/ 48( 12%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
06: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\jiaotongdeng\jtd1.rpt
jtd1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk
Device-Specific Information: e:\eda\jiaotongdeng\jtd1.rpt
jtd1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: e:\eda\jiaotongdeng\jtd1.rpt
jtd1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC2_C24, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC1_C24, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !count0 & count1
# count0 & !count1;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC1_C21, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !count1 & count2
# !count0 & count2
# count0 & count1 & !count2;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC2_C21, type is buried.
count3 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !count1 & count3
# !count0 & count3
# !count2 & count3
# count0 & count1 & count2 & !count3;
-- Node name is 'led7s0'
-- Equation name is 'led7s0', type is output
led7s0 = _LC2_C15;
-- Node name is 'led7s1'
-- Equation name is 'led7s1', type is output
led7s1 = _LC4_C15;
-- Node name is 'led7s2'
-- Equation name is 'led7s2', type is output
led7s2 = !_LC5_C21;
-- Node name is 'led7s3'
-- Equation name is 'led7s3', type is output
led7s3 = _LC3_C15;
-- Node name is 'led7s4'
-- Equation name is 'led7s4', type is output
led7s4 = _LC7_C21;
-- Node name is 'led7s5'
-- Equation name is 'led7s5', type is output
led7s5 = _LC3_C21;
-- Node name is 'led7s6'
-- Equation name is 'led7s6', type is output
led7s6 = _LC6_C21;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC3_C6;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC8_C6;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC5_C6;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC7_C5;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC1_C5;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC5_C5;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC8_C5;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC2_C5;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC7_C6;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC3_C5;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC4_C5;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC6_C5;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC4_C24, type is buried.
state0 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = _LC6_C24 & !state0 & !state1
# _LC6_C24 & !state0 & !state2
# !_LC6_C24 & state0;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC5_C24, type is buried.
state1 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = _LC6_C24 & state0 & !state1 & !state2
# !state0 & state1 & !state2
# !_LC6_C24 & state1;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC3_C24, type is buried.
state2 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !state0 & !state1 & state2
# _LC6_C24 & state0 & state1 & !state2
# !_LC6_C24 & state2;
-- Node name is ':405'
-- Equation name is '_LC6_C24', type is buried
!_LC6_C24 = _LC6_C24~NOT;
_LC6_C24~NOT = LCELL( _EQ007);
_EQ007 = !count1
# !count0
# !count3
# count2;
-- Node name is ':683'
-- Equation name is '_LC5_C6', type is buried
!_LC5_C6 = _LC5_C6~NOT;
_LC5_C6~NOT = LCELL( _EQ008);
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