📄 fuza03.rpt
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# _LC6_F4;
-- Node name is ':652'
-- Equation name is '_LC7_F4', type is buried
_LC7_F4 = LCELL( _EQ017);
_EQ017 = !state0 & state2
# !state1 & state2
# !_LC3_F8 & state0 & state1 & !state2
# _LC3_F8 & state2;
-- Node name is ':658'
-- Equation name is '_LC8_F4', type is buried
_LC8_F4 = LCELL( _EQ018);
_EQ018 = _LC5_F4 & !_LC8_A3
# !_LC6_F4 & _LC7_F4 & _LC8_A3;
-- Node name is ':664'
-- Equation name is '_LC1_F5', type is buried
_LC1_F5 = LCELL( _EQ019);
_EQ019 = !_LC3_F8 & state0 & !state1
# !state0 & state1
# _LC3_F8 & state1;
-- Node name is ':670'
-- Equation name is '_LC6_F5', type is buried
_LC6_F5 = LCELL( _EQ020);
_EQ020 = _LC1_F5 & !_LC6_F4 & _LC8_A3
# _LC4_F5 & !_LC8_A3;
-- Node name is '~679~1'
-- Equation name is '~679~1', location is LC7_F8, type is buried.
-- synthesized logic cell
_LC7_F8 = LCELL( _EQ021);
_EQ021 = count2 & count3 & !state0
# count3 & _LC2_F2 & !state0
# !count3 & state0
# !count2 & !_LC2_F2 & state0;
-- Node name is '~727~1'
-- Equation name is '~727~1', location is LC7_F5, type is buried.
-- synthesized logic cell
_LC7_F5 = LCELL( _EQ022);
_EQ022 = state0 & state2
# state1 & state2
# _LC3_F4 & !state0 & !state2;
-- Node name is '~1014~1'
-- Equation name is '~1014~1', location is LC4_A2, type is buried.
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ023);
_EQ023 = state2
# state0 & state1;
-- Node name is '~1014~2'
-- Equation name is '~1014~2', location is LC1_A3, type is buried.
-- synthesized logic cell
_LC1_A3 = LCELL( _EQ024);
_EQ024 = state2
# state0 & state1;
-- Node name is '~1014~3'
-- Equation name is '~1014~3', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( _EQ025);
_EQ025 = state2
# state0 & state1;
-- Node name is ':1014'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ026);
_EQ026 = state2
# state0 & state1;
-- Node name is '~1074~1'
-- Equation name is '~1074~1', location is LC2_A2, type is buried.
-- synthesized logic cell
_LC2_A2 = LCELL( _EQ027);
_EQ027 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~1074~2'
-- Equation name is '~1074~2', location is LC3_A3, type is buried.
-- synthesized logic cell
_LC3_A3 = LCELL( _EQ028);
_EQ028 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~1074~3'
-- Equation name is '~1074~3', location is LC6_A3, type is buried.
-- synthesized logic cell
_LC6_A3 = LCELL( _EQ029);
_EQ029 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':1074'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ030);
_EQ030 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':1355'
-- Equation name is '_LC5_F8', type is buried
_LC5_F8 = LCELL( _EQ031);
_EQ031 = !count1 & !count2 & count3
# count0 & !count1 & count2 & !count3
# !count0 & count1 & !count3
# count1 & !count2 & !count3;
-- Node name is '~1364~1'
-- Equation name is '~1364~1', location is LC5_F3, type is buried.
-- synthesized logic cell
_LC5_F3 = LCELL( _EQ032);
_EQ032 = count1
# !count0
# count2;
-- Node name is ':1364'
-- Equation name is '_LC7_F3', type is buried
!_LC7_F3 = _LC7_F3~NOT;
_LC7_F3~NOT = LCELL( _EQ033);
_EQ033 = _LC5_F3
# count3;
-- Node name is ':1376'
-- Equation name is '_LC4_F8', type is buried
_LC4_F8 = LCELL( _EQ034);
_EQ034 = !count0 & !count1 & !count2 & !count3;
-- Node name is ':1381'
-- Equation name is '_LC8_F8', type is buried
_LC8_F8 = LCELL( _EQ035);
_EQ035 = !_LC4_F8 & _LC5_F3 & _LC5_F8
# count3 & !_LC4_F8 & _LC5_F8;
-- Node name is ':1415'
-- Equation name is '_LC1_F3', type is buried
_LC1_F3 = LCELL( _EQ036);
_EQ036 = !count0 & !count1 & !count2 & !count3
# count2 & count3
# count0 & count2
# count1 & count2
# count0 & count1;
-- Node name is ':1451'
-- Equation name is '_LC2_F3', type is buried
_LC2_F3 = LCELL( _EQ037);
_EQ037 = count2 & count3
# count0 & count3
# count0 & count1 & !count2
# count1 & !count2 & !count3
# !count0 & !count2 & !count3
# count0 & !count1 & count2;
-- Node name is ':1472'
-- Equation name is '_LC6_F3', type is buried
_LC6_F3 = LCELL( _EQ038);
_EQ038 = !count1
# !count0 & count2
# count2 & count3
# count0 & !count2
# count0 & count3
# !count0 & !count3
# !count2 & !count3;
-- Node name is ':1487'
-- Equation name is '_LC4_F3', type is buried
_LC4_F3 = LCELL( _EQ039);
_EQ039 = count2 & count3
# count0 & count3
# !count1 & count3
# !count0 & count1 & count2
# !count0 & count1 & !count3
# count0 & count1 & !count2
# count1 & !count2 & !count3
# !count0 & !count2 & !count3
# !count0 & !count1 & !count2
# count0 & !count1 & count2;
-- Node name is ':1523'
-- Equation name is '_LC6_F8', type is buried
_LC6_F8 = LCELL( _EQ040);
_EQ040 = !count3 & !_LC5_F3
# _LC4_F8
# !_LC3_F4 & _LC5_F3
# !count3 & !_LC3_F4;
-- Node name is ':1559'
-- Equation name is '_LC4_F2', type is buried
_LC4_F2 = LCELL( _EQ041);
_EQ041 = count3
# !count2
# count0 & count1
# !count0 & !count1;
-- Node name is '~1589~1'
-- Equation name is '~1589~1', location is LC8_F3, type is buried.
-- synthesized logic cell
_LC8_F3 = LCELL( _EQ042);
_EQ042 = !count0 & !count1 & count2 & !count3
# count1 & !count2 & !count3;
-- Node name is ':1595'
-- Equation name is '_LC3_F3', type is buried
_LC3_F3 = LCELL( _EQ043);
_EQ043 = _LC4_F8
# _LC6_F3 & !_LC7_F3
# !_LC7_F3 & _LC8_F3;
-- Node name is ':1846'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ044);
_EQ044 = clk & !state0 & !state2;
-- Node name is ':1919'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ045);
_EQ045 = clk & state2
# clk & !state0 & !state1;
-- Node name is ':1992'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ046);
_EQ046 = clk & !state0 & !state2;
-- Node name is ':2065'
-- Equation name is '_LC2_A3', type is buried
_LC2_A3 = LCELL( _EQ047);
_EQ047 = clk & state2
# clk & !state0 & !state1;
Project Information h:\jiaotongdeng\fuza03.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,471K
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