📄 fuza03.rpt
字号:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\jiaotongdeng\fuza03.rpt
fuza03
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - F 02 OR2 ! 0 2 0 4 |LPM_ADD_SUB:425|addcore:adder|:59
- 2 - F 08 DFFE + 1 3 0 14 count3 (:22)
- 1 - F 08 DFFE + 1 2 0 13 count2 (:23)
- 2 - F 04 DFFE + 1 3 0 12 count1 (:24)
- 8 - F 05 DFFE + 1 3 0 13 count0 (:25)
- 1 - F 04 DFFE + 1 3 0 18 state2 (:26)
- 3 - F 05 DFFE + 1 3 0 17 state1 (:27)
- 5 - F 05 DFFE + 1 4 0 22 state0 (:28)
- 8 - A 03 AND2 s ! 0 2 0 6 ~448~1
- 6 - F 04 AND2 0 4 0 6 :465
- 3 - F 08 OR2 0 3 0 5 :470
- 3 - F 04 AND2 0 4 0 5 :497
- 5 - F 04 OR2 0 4 0 1 :534
- 4 - F 05 OR2 0 3 0 1 :540
- 2 - F 05 OR2 s 0 3 0 2 ~610~1
- 4 - F 04 OR2 0 4 0 1 :631
- 7 - F 04 OR2 0 4 0 1 :652
- 8 - F 04 OR2 0 4 0 1 :658
- 1 - F 05 OR2 0 3 0 1 :664
- 6 - F 05 OR2 0 4 0 1 :670
- 7 - F 08 OR2 s 0 4 0 1 ~679~1
- 7 - F 05 OR2 s 0 4 0 1 ~727~1
- 4 - A 02 OR2 s 0 3 1 0 ~1014~1
- 1 - A 03 OR2 s 0 3 1 0 ~1014~2
- 1 - A 02 OR2 s 0 3 1 0 ~1014~3
- 7 - A 03 OR2 0 3 1 0 :1014
- 2 - A 02 OR2 s 0 3 1 0 ~1074~1
- 3 - A 03 OR2 s 0 3 1 0 ~1074~2
- 6 - A 03 OR2 s 0 3 1 0 ~1074~3
- 5 - A 03 OR2 0 3 1 0 :1074
- 5 - F 08 OR2 0 4 0 1 :1355
- 5 - F 03 OR2 s 0 3 0 3 ~1364~1
- 7 - F 03 OR2 ! 0 2 0 1 :1364
- 4 - F 08 AND2 0 4 0 3 :1376
- 8 - F 08 OR2 0 4 1 0 :1381
- 1 - F 03 OR2 0 4 1 0 :1415
- 2 - F 03 OR2 0 4 1 0 :1451
- 6 - F 03 OR2 0 4 0 1 :1472
- 4 - F 03 OR2 0 4 1 0 :1487
- 6 - F 08 OR2 0 4 1 0 :1523
- 4 - F 02 OR2 0 4 1 0 :1559
- 8 - F 03 OR2 s 0 4 0 1 ~1589~1
- 3 - F 03 OR2 0 4 1 0 :1595
- 4 - A 03 AND2 1 2 1 0 :1846
- 8 - A 02 OR2 1 3 1 0 :1919
- 3 - A 02 AND2 1 2 1 0 :1992
- 2 - A 03 OR2 1 3 1 0 :2065
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\fuza03.rpt
fuza03
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 3/ 96( 3%) 19/ 48( 39%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\fuza03.rpt
fuza03
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: h:\jiaotongdeng\fuza03.rpt
fuza03
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: h:\jiaotongdeng\fuza03.rpt
fuza03
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC8_F5, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = _LC6_F4 & _LC8_A3
# !count0 & !_LC8_A3
# !count0 & _LC3_F8;
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC2_F4, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = _LC4_F4 & _LC8_A3
# !count0 & count1 & !_LC8_A3
# count0 & !count1 & !_LC8_A3;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC1_F8, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = count2 & !_LC2_F2 & _LC2_F5
# !count2 & _LC2_F2 & _LC2_F5;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC2_F8, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = !count2 & count3 & _LC2_F5
# count3 & !_LC2_F2 & _LC2_F5
# count2 & !count3 & _LC2_F2 & _LC2_F5;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC3_F3;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC4_F2;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC6_F8;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC4_F3;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC2_F3;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC1_F3;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC8_F8;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC7_A3;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC5_A3;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC4_A3;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC2_A2;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC4_A2;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC8_A2;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC1_A3;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC3_A3;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC3_A2;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC6_A3;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC1_A2;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC2_A3;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC5_F5, type is buried.
state0 = DFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = _LC7_F8 & _LC8_A3
# _LC6_F4 & _LC8_A3
# _LC7_F5;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC3_F5, type is buried.
state1 = DFFE( _EQ006, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = _LC6_F5 & !state0 & !state1
# _LC6_F5 & !state2;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC1_F4, type is buried.
state2 = DFFE( _EQ007, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = _LC8_F4 & !state2
# _LC8_F4 & !state0 & !state1;
-- Node name is '|LPM_ADD_SUB:425|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_F2', type is buried
!_LC2_F2 = _LC2_F2~NOT;
_LC2_F2~NOT = LCELL( _EQ008);
_EQ008 = !count1
# !count0;
-- Node name is '~448~1'
-- Equation name is '~448~1', location is LC8_A3, type is buried.
-- synthesized logic cell
!_LC8_A3 = _LC8_A3~NOT;
_LC8_A3~NOT = LCELL( _EQ009);
_EQ009 = !state0 & !state2;
-- Node name is ':465'
-- Equation name is '_LC6_F4', type is buried
_LC6_F4 = LCELL( _EQ010);
_EQ010 = _LC3_F4 & !state0 & !state1 & state2;
-- Node name is ':470'
-- Equation name is '_LC3_F8', type is buried
_LC3_F8 = LCELL( _EQ011);
_EQ011 = !count3
# !count2 & !_LC2_F2;
-- Node name is ':497'
-- Equation name is '_LC3_F4', type is buried
_LC3_F4 = LCELL( _EQ012);
_EQ012 = !count0 & count1 & !count2 & !count3;
-- Node name is ':534'
-- Equation name is '_LC5_F4', type is buried
_LC5_F4 = LCELL( _EQ013);
_EQ013 = !state0 & state2
# !state1 & state2
# _LC3_F4 & state0 & state1 & !state2
# !_LC3_F4 & state2;
-- Node name is ':540'
-- Equation name is '_LC4_F5', type is buried
_LC4_F5 = LCELL( _EQ014);
_EQ014 = _LC3_F4 & state0 & !state1
# !state0 & state1
# !_LC3_F4 & state1;
-- Node name is '~610~1'
-- Equation name is '~610~1', location is LC2_F5, type is buried.
-- synthesized logic cell
_LC2_F5 = LCELL( _EQ015);
_EQ015 = _LC3_F8 & !_LC6_F4
# !_LC8_A3;
-- Node name is ':631'
-- Equation name is '_LC4_F4', type is buried
_LC4_F4 = LCELL( _EQ016);
_EQ016 = !count0 & count1 & _LC3_F8
# count0 & !count1 & _LC3_F8
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