weizhi.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

-- Equation name is '~1542~1', location is LC1_A5, type is buried.
-- synthesized logic cell 
!_LC1_A5 = _LC1_A5~NOT;
_LC1_A5~NOT = LCELL( _EQ033);
  _EQ033 = !state~5
         # !state~2 & !state~4
         #  state~3 & !state~4;

-- Node name is '~1542~2' 
-- Equation name is '~1542~2', location is LC7_A4, type is buried.
-- synthesized logic cell 
_LC7_A4  = LCELL( _EQ034);
  _EQ034 =  _LC1_A4 & !_LC6_A8
         #  _LC1_A5 & !state~5
         #  _LC1_A4 & !state~5;

-- Node name is '~1542~3' 
-- Equation name is '~1542~3', location is LC8_A4, type is buried.
-- synthesized logic cell 
_LC8_A4  = LCELL( _EQ035);
  _EQ035 = !sl0 & !sl1 & !sl2 & !sl3
         #  sl0 &  sl3
         #  sl1 &  sl3
         #  sl2 &  sl3;

-- Node name is '~1572~1' 
-- Equation name is '~1572~1', location is LC6_A4, type is buried.
-- synthesized logic cell 
_LC6_A4  = LCELL( _EQ036);
  _EQ036 = !sl0 & !sl1
         #  sl0 &  sl1;

-- Node name is '~1587~1' 
-- Equation name is '~1587~1', location is LC7_A8, type is buried.
-- synthesized logic cell 
_LC7_A8  = LCELL( _EQ037);
  _EQ037 =  _LC1_A5 &  _LC2_A2;

-- Node name is '~1607~1' 
-- Equation name is '~1607~1', location is LC4_A2, type is buried.
-- synthesized logic cell 
_LC4_A2  = LCELL( _EQ038);
  _EQ038 = !state~5
         #  state~1;

-- Node name is '~1652~1' 
-- Equation name is '~1652~1', location is LC2_A5, type is buried.
-- synthesized logic cell 
_LC2_A5  = LCELL( _EQ039);
  _EQ039 =  _LC1_A4 & !state~2 & !state~4
         #  _LC1_A4 &  state~3 & !state~4;

-- Node name is '~1652~2' 
-- Equation name is '~1652~2', location is LC3_A6, type is buried.
-- synthesized logic cell 
_LC3_A6  = LCELL( _EQ040);
  _EQ040 =  sh1
         #  _LC1_A6 &  _LC2_A2 & !sh0;

-- Node name is '~1652~3' 
-- Equation name is '~1652~3', location is LC4_A6, type is buried.
-- synthesized logic cell 
_LC4_A6  = LCELL( _EQ041);
  _EQ041 = !_LC6_A8 &  sh0
         # !_LC1_A4;

-- Node name is '~1652~4' 
-- Equation name is '~1652~4', location is LC5_A6, type is buried.
-- synthesized logic cell 
_LC5_A6  = LCELL( _EQ042);
  _EQ042 =  state~2 & !state~3 &  state~5
         #  _LC1_A4;

-- Node name is '~1652~5' 
-- Equation name is '~1652~5', location is LC7_A6, type is buried.
-- synthesized logic cell 
_LC7_A6  = LCELL( _EQ043);
  _EQ043 =  _LC5_A6 & !state~5
         #  _LC2_A2 & !_LC2_A6 &  _LC5_A6;

-- Node name is ':1794' 
-- Equation name is '_LC5_A2', type is buried 
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ044);
  _EQ044 =  cnt2
         #  cnt1
         # !cnt0;

-- Node name is ':1802' 
-- Equation name is '_LC6_A8', type is buried 
_LC6_A8  = LCELL( _EQ045);
  _EQ045 = !_LC2_A6 & !sh2 & !sh3;

-- Node name is ':2360' 
-- Equation name is '_LC4_A8', type is buried 
_LC4_A8  = LCELL( _EQ046);
  _EQ046 =  _LC5_A2 &  sh3
         # !_LC5_A2 &  sl3;

-- Node name is ':2366' 
-- Equation name is '_LC2_A8', type is buried 
!_LC2_A8 = _LC2_A8~NOT;
_LC2_A8~NOT = LCELL( _EQ047);
  _EQ047 =  _LC5_A2 & !sh2
         # !_LC5_A2 & !sl2
         # !sh2 & !sl2;

-- Node name is ':2372' 
-- Equation name is '_LC6_A6', type is buried 
!_LC6_A6 = _LC6_A6~NOT;
_LC6_A6~NOT = LCELL( _EQ048);
  _EQ048 = !_LC5_A2 & !sl1
         #  _LC5_A2 & !sh1
         # !sh1 & !sl1;

-- Node name is ':2378' 
-- Equation name is '_LC1_A2', type is buried 
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ049);
  _EQ049 =  _LC5_A2 & !sh0
         # !_LC5_A2 & !sl0
         # !sh0 & !sl0;

-- Node name is ':2504' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ050);
  _EQ050 =  _LC1_A2 &  _LC2_A8 & !_LC4_A8
         # !_LC4_A8 &  _LC6_A6
         # !_LC2_A8 &  _LC4_A8 & !_LC6_A6
         # !_LC1_A2 & !_LC2_A8 & !_LC4_A8;

-- Node name is ':2537' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ051);
  _EQ051 = !_LC2_A8 & !_LC6_A6
         #  _LC1_A2 & !_LC4_A8 &  _LC6_A6
         # !_LC1_A2 & !_LC4_A8 & !_LC6_A6
         # !_LC2_A8 & !_LC4_A8;

-- Node name is ':2570' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ052);
  _EQ052 =  _LC1_A2 & !_LC4_A8
         # !_LC4_A8 & !_LC6_A6
         # !_LC2_A8 & !_LC6_A6
         #  _LC2_A8 & !_LC4_A8;

-- Node name is ':2603' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ053);
  _EQ053 = !_LC1_A2 & !_LC2_A8 & !_LC4_A8
         # !_LC2_A8 & !_LC4_A8 &  _LC6_A6
         #  _LC1_A2 &  _LC2_A8 & !_LC4_A8 & !_LC6_A6
         # !_LC1_A2 & !_LC4_A8 &  _LC6_A6
         # !_LC1_A2 & !_LC2_A8 & !_LC6_A6
         # !_LC2_A8 &  _LC4_A8 & !_LC6_A6;

-- Node name is ':2636' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ054);
  _EQ054 = !_LC1_A2 & !_LC2_A8 & !_LC4_A8
         # !_LC1_A2 & !_LC2_A8 & !_LC6_A6
         # !_LC1_A2 & !_LC4_A8 &  _LC6_A6;

-- Node name is ':2669' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ055);
  _EQ055 = !_LC1_A2 & !_LC4_A8 & !_LC6_A6
         #  _LC2_A8 & !_LC4_A8 & !_LC6_A6
         # !_LC1_A2 &  _LC2_A8 & !_LC4_A8
         # !_LC1_A2 & !_LC2_A8 & !_LC6_A6
         # !_LC2_A8 &  _LC4_A8 & !_LC6_A6;

-- Node name is ':2704' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ056);
  _EQ056 = !_LC2_A8 & !_LC4_A8 &  _LC6_A6
         #  _LC2_A8 & !_LC4_A8 & !_LC6_A6
         # !_LC1_A2 & !_LC4_A8 &  _LC6_A6
         # !_LC2_A8 &  _LC4_A8 & !_LC6_A6;



Project Information                                 e:\jiaotongdeng\weizhi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,810K