📄 weizhi.rpt
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Total input I/O cell registers required: 0
Total output pins required: 22
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 59
Total flipflops required: 28
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 12/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 1 8 0 8 8 8 8 8 0 3 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 59/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 1 8 0 8 8 8 8 8 0 3 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 59/0
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk1
43 - - - -- INPUT G 0 0 0 0 clk2
2 - - - -- INPUT G 0 0 0 1 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
71 - - A -- OUTPUT 0 1 0 0 led0
69 - - A -- OUTPUT 0 1 0 0 led1
72 - - A -- OUTPUT 0 1 0 0 led2
70 - - A -- OUTPUT 0 1 0 0 led3
53 - - - 20 OUTPUT 0 1 0 0 led4
52 - - - 19 OUTPUT 0 1 0 0 led5
24 - - B -- OUTPUT 0 1 0 0 led6
28 - - C -- OUTPUT 0 1 0 0 q0
25 - - B -- OUTPUT 0 1 0 0 q1
5 - - - 05 OUTPUT 0 1 0 0 q2
19 - - A -- OUTPUT 0 1 0 0 q3
38 - - - 10 OUTPUT 0 1 0 0 q4
18 - - A -- OUTPUT 0 1 0 0 q5
60 - - C -- OUTPUT 0 1 0 0 q6
36 - - - 07 OUTPUT 0 1 0 0 q7
35 - - - 06 OUTPUT 0 1 0 0 q8
22 - - B -- OUTPUT 0 1 0 0 q9
21 - - B -- OUTPUT 0 1 0 0 q10
17 - - A -- OUTPUT 0 1 0 0 q11
9 - - - 02 OUTPUT 0 1 0 0 sel0
11 - - - 01 OUTPUT 0 1 0 0 sel1
10 - - - 01 OUTPUT 0 1 0 0 sel2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 06 AND2 ! 0 2 0 4 |LPM_ADD_SUB:582|addcore:adder|pcarry1
- 5 - A 08 OR2 0 2 0 1 |LPM_ADD_SUB:582|addcore:adder|pcarry2
- 2 - A 10 SOFT s ! 1 0 0 12 rst~1
- 7 - A 02 DFFE + 0 3 0 1 state~1
- 4 - A 05 DFFE + 0 3 0 8 state~2
- 5 - A 05 DFFE + 0 3 0 9 state~3
- 6 - A 05 DFFE + 0 3 0 11 state~4
- 1 - A 01 DFFE + 0 1 0 16 state~5
- 8 - A 08 DFFE + 0 3 0 2 sh3 (:26)
- 3 - A 08 DFFE + 0 3 0 3 sh2 (:27)
- 8 - A 06 DFFE + 0 4 0 3 sh1 (:28)
- 1 - A 08 DFFE + 0 2 0 4 sh0 (:29)
- 4 - A 04 DFFE + 0 4 0 3 sl3 (:30)
- 2 - A 04 DFFE + 0 3 0 3 sl2 (:31)
- 5 - A 04 DFFE + ! 0 4 0 5 sl1 (:32)
- 3 - A 04 DFFE + 0 3 0 5 sl0 (:33)
- 7 - A 05 DFFE + 0 4 1 0 y_ewsn3 (:34)
- 8 - A 05 DFFE + 0 4 1 0 y_ewsn2 (:35)
- 5 - A 07 DFFE + 0 4 1 0 y_ewsn1 (:36)
- 3 - A 07 DFFE + 0 4 1 0 y_ewsn0 (:37)
- 8 - A 07 DFFE + 0 3 1 0 g_ewsn3 (:38)
- 6 - A 07 DFFE + 0 3 1 0 g_ewsn2 (:39)
- 3 - A 10 DFFE + 0 2 1 0 g_ewsn1 (:40)
- 1 - A 10 DFFE + 0 2 1 0 g_ewsn0 (:41)
- 3 - A 05 DFFE + 0 4 1 0 r_ewsn3 (:42)
- 4 - A 07 DFFE + 0 3 1 0 r_ewsn2 (:43)
- 7 - A 07 DFFE + 0 4 1 0 r_ewsn1 (:44)
- 2 - A 07 DFFE + 0 3 1 0 r_ewsn0 (:45)
- 6 - A 02 DFFE + 0 3 1 1 cnt2 (:46)
- 3 - A 02 DFFE + 0 3 1 2 cnt1 (:47)
- 8 - A 02 DFFE + 0 1 1 3 cnt0 (:48)
- 2 - A 02 AND2 0 2 0 3 :733
- 1 - A 04 AND2 0 4 0 17 :1240
- 1 - A 06 AND2 0 2 0 1 :1424
- 1 - A 07 AND2 ! 0 2 0 4 :1509
- 1 - A 05 OR2 s ! 0 4 0 4 ~1542~1
- 7 - A 04 OR2 s 0 4 0 1 ~1542~2
- 8 - A 04 OR2 s 0 4 0 1 ~1542~3
- 6 - A 04 OR2 s 0 2 0 1 ~1572~1
- 7 - A 08 AND2 s 0 2 0 4 ~1587~1
- 4 - A 02 OR2 s 0 2 0 1 ~1607~1
- 2 - A 05 OR2 s 0 4 0 2 ~1652~1
- 3 - A 06 OR2 s 0 4 0 1 ~1652~2
- 4 - A 06 OR2 s 0 3 0 1 ~1652~3
- 5 - A 06 OR2 s 0 4 0 1 ~1652~4
- 7 - A 06 OR2 s 0 4 0 1 ~1652~5
- 5 - A 02 OR2 ! 0 3 0 5 :1794
- 6 - A 08 AND2 0 3 0 11 :1802
- 4 - A 08 OR2 0 3 0 7 :2360
- 2 - A 08 OR2 ! 0 3 0 7 :2366
- 6 - A 06 OR2 ! 0 3 0 7 :2372
- 1 - A 02 OR2 ! 0 3 0 7 :2378
- 6 - A 20 OR2 0 4 1 0 :2504
- 1 - A 20 OR2 0 4 1 0 :2537
- 7 - A 20 OR2 0 4 1 0 :2570
- 5 - A 20 OR2 0 4 1 0 :2603
- 3 - A 20 OR2 0 4 1 0 :2636
- 8 - A 20 OR2 0 4 1 0 :2669
- 4 - A 20 OR2 0 4 1 0 :2704
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 21/ 48( 43%) 4/ 48( 8%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 clk1
INPUT 3 clk2
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 14 rst
Device-Specific Information: e:\jiaotongdeng\weizhi.rpt
weizhi
** EQUATIONS **
clk1 : INPUT;
clk2 : INPUT;
rst : INPUT;
-- Node name is ':48' = 'cnt0'
-- Equation name is 'cnt0', location is LC8_A2, type is buried.
cnt0 = DFFE( _EQ001, GLOBAL( clk2), VCC, VCC, VCC);
_EQ001 = !cnt0 & !_LC6_A8;
-- Node name is ':47' = 'cnt1'
-- Equation name is 'cnt1', location is LC3_A2, type is buried.
cnt1 = DFFE( _EQ002, GLOBAL( clk2), VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt1 & !_LC5_A2 & !_LC6_A8
# cnt0 & !cnt1 & !_LC5_A2 & !_LC6_A8;
-- Node name is ':46' = 'cnt2'
-- Equation name is 'cnt2', location is LC6_A2, type is buried.
cnt2 = DFFE( _EQ003, GLOBAL( clk2), VCC, VCC, VCC);
_EQ003 = !cnt1 & cnt2 & !_LC6_A8
# !cnt0 & cnt2 & !_LC6_A8
# cnt0 & cnt1 & !cnt2 & !_LC6_A8;
-- Node name is ':41' = 'g_ewsn0'
-- Equation name is 'g_ewsn0', location is LC1_A10, type is buried.
g_ewsn0 = DFFE( state~2, GLOBAL( clk1), VCC, VCC, !_LC2_A10);
-- Node name is ':40' = 'g_ewsn1'
-- Equation name is 'g_ewsn1', location is LC3_A10, type is buried.
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