fuza02.rpt

交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.

         # !_LC3_F2 &  _LC4_F8 &  state2
         #  _LC3_F2 &  _LC4_F8 &  _LC8_F8 & !state2;

-- Node name is '|LPM_ADD_SUB:330|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_F1', type is buried 
_LC3_F1  = LCELL( _EQ008);
  _EQ008 =  count2
         #  count1
         #  count0;

-- Node name is '|LPM_ADD_SUB:330|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_F3', type is buried 
_LC5_F3  = LCELL( _EQ009);
  _EQ009 = !count0 &  count1
         #  count0 & !count1;

-- Node name is '|LPM_ADD_SUB:381|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F8', type is buried 
_LC8_F8  = LCELL( _EQ010);
  _EQ010 =  state0 &  state1;

-- Node name is '~353~1' 
-- Equation name is '~353~1', location is LC8_A3, type is buried.
-- synthesized logic cell 
!_LC8_A3 = _LC8_A3~NOT;
_LC8_A3~NOT = LCELL( _EQ011);
  _EQ011 = !state0 & !state2;

-- Node name is ':363' 
-- Equation name is '_LC3_F2', type is buried 
!_LC3_F2 = _LC3_F2~NOT;
_LC3_F2~NOT = LCELL( _EQ012);
  _EQ012 =  count3
         #  _LC3_F1;

-- Node name is ':480' 
-- Equation name is '_LC5_F8', type is buried 
_LC5_F8  = LCELL( _EQ013);
  _EQ013 =  _LC7_F1 & !state0 & !state1 &  state2;

-- Node name is '~683~1' 
-- Equation name is '~683~1', location is LC4_F3, type is buried.
-- synthesized logic cell 
_LC4_F3  = LCELL( _EQ014);
  _EQ014 = !_LC3_F2 & !_LC5_F8
         # !_LC3_F2 & !_LC8_A3;

-- Node name is '~736~1' 
-- Equation name is '~736~1', location is LC4_F8, type is buried.
-- synthesized logic cell 
_LC4_F8  = LCELL( _EQ015);
  _EQ015 = !state2
         # !_LC7_F1 & !state0 & !state1;

-- Node name is '~740~1' 
-- Equation name is '~740~1', location is LC7_F8, type is buried.
-- synthesized logic cell 
_LC7_F8  = LCELL( _EQ016);
  _EQ016 =  _LC5_F8 &  state2
         #  _LC5_F8 &  state0
         #  state1 &  state2
         #  state0 &  state2;

-- Node name is '~1082~1' 
-- Equation name is '~1082~1', location is LC4_B2, type is buried.
-- synthesized logic cell 
_LC4_B2  = LCELL( _EQ017);
  _EQ017 =  state2
         #  state0 &  state1;

-- Node name is '~1082~2' 
-- Equation name is '~1082~2', location is LC1_F8, type is buried.
-- synthesized logic cell 
_LC1_F8  = LCELL( _EQ018);
  _EQ018 =  state2
         #  state0 &  state1;

-- Node name is '~1082~3' 
-- Equation name is '~1082~3', location is LC1_B2, type is buried.
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ019);
  _EQ019 =  state2
         #  state0 &  state1;

-- Node name is ':1082' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ020);
  _EQ020 =  state2
         #  state0 &  state1;

-- Node name is '~1142~1' 
-- Equation name is '~1142~1', location is LC2_B2, type is buried.
-- synthesized logic cell 
_LC2_B2  = LCELL( _EQ021);
  _EQ021 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~1142~2' 
-- Equation name is '~1142~2', location is LC3_A3, type is buried.
-- synthesized logic cell 
_LC3_A3  = LCELL( _EQ022);
  _EQ022 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is '~1142~3' 
-- Equation name is '~1142~3', location is LC6_A3, type is buried.
-- synthesized logic cell 
_LC6_A3  = LCELL( _EQ023);
  _EQ023 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1142' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ024);
  _EQ024 =  state0 & !state1 & !state2
         # !state0 &  state1 & !state2;

-- Node name is ':1447' 
-- Equation name is '_LC7_F1', type is buried 
_LC7_F1  = LCELL( _EQ025);
  _EQ025 = !count0 &  count1 & !count2 & !count3;

-- Node name is ':1476' 
-- Equation name is '_LC8_F1', type is buried 
_LC8_F1  = LCELL( _EQ026);
  _EQ026 =  count3
         # !count1 &  count2
         #  count1 & !count2
         # !count0 &  count1
         # !count0 &  count2;

-- Node name is ':1501' 
-- Equation name is '_LC1_F1', type is buried 
_LC1_F1  = LCELL( _EQ027);
  _EQ027 =  count3
         # !count1 &  count2
         # !count0 &  count2
         # !count0 & !count1;

-- Node name is ':1528' 
-- Equation name is '_LC2_F1', type is buried 
_LC2_F1  = LCELL( _EQ028);
  _EQ028 =  count3
         # !count0 & !count2
         # !count0 &  count1;

-- Node name is ':1555' 
-- Equation name is '_LC4_F1', type is buried 
_LC4_F1  = LCELL( _EQ029);
  _EQ029 =  count3
         # !count0 &  count1
         # !count0 & !count2
         #  count1 & !count2
         #  count0 & !count1 &  count2;

-- Node name is ':1609' 
-- Equation name is '_LC6_F1', type is buried 
_LC6_F1  = LCELL( _EQ030);
  _EQ030 =  count3
         # !count2
         # !count0 & !count1
         #  count0 &  count1;

-- Node name is ':1636' 
-- Equation name is '_LC2_F3', type is buried 
_LC2_F3  = LCELL( _EQ031);
  _EQ031 = !count3 & !_LC3_F1
         #  _LC5_F1;

-- Node name is ':1638' 
-- Equation name is '_LC5_F1', type is buried 
_LC5_F1  = LCELL( _EQ032);
  _EQ032 =  count1
         #  count3
         #  count0 &  count2
         # !count0 & !count2;

-- Node name is ':1849' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ033);
  _EQ033 =  clk & !state0 & !state2;

-- Node name is ':1922' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ034);
  _EQ034 =  clk &  state2
         #  clk & !state0 & !state1;

-- Node name is ':1995' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = LCELL( _EQ035);
  _EQ035 =  clk & !state0 & !state2;

-- Node name is ':2068' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ036);
  _EQ036 =  clk &  state2
         #  clk & !state0 & !state1;



Project Information                                 h:\jiaotongdeng\fuza02.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,692K