📄 fuza01.rpt
字号:
81 - - F -- OUTPUT 0 1 0 0 led7s5
82 - - E -- OUTPUT 0 1 0 0 led7s6
116 - - - 04 OUTPUT 0 1 0 0 pout1
114 - - - 04 OUTPUT 0 1 0 0 pout2
113 - - - 03 OUTPUT 0 1 0 0 pout3
112 - - - 02 OUTPUT 0 1 0 0 pout4
111 - - - 01 OUTPUT 0 1 0 0 pout5
110 - - - 01 OUTPUT 0 1 0 0 pout6
109 - - A -- OUTPUT 0 1 0 0 pout7
102 - - A -- OUTPUT 0 1 0 0 pout8
101 - - A -- OUTPUT 0 1 0 0 pout9
100 - - A -- OUTPUT 0 1 0 0 pout10
99 - - B -- OUTPUT 0 1 0 0 pout11
98 - - B -- OUTPUT 0 1 0 0 pout12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\jiaotongdeng\fuza01.rpt
fuza01
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 10 AND2 0 3 0 1 |LPM_ADD_SUB:330|addcore:adder|:63
- 2 - F 10 DFFE + 1 3 0 12 count3 (:22)
- 3 - F 10 DFFE + 1 3 0 9 count2 (:23)
- 4 - F 10 DFFE + 1 2 0 10 count1 (:24)
- 1 - F 10 DFFE + 1 1 0 11 count0 (:25)
- 1 - F 09 DFFE + 1 3 0 18 state2 (:26)
- 2 - F 09 DFFE + 1 3 0 17 state1 (:27)
- 7 - F 10 DFFE + 1 4 0 22 state0 (:28)
- 6 - F 04 AND2 s ! 0 2 0 5 ~353~1
- 7 - F 03 OR2 ! 0 4 1 5 :363
- 7 - F 09 OR2 0 4 0 1 :408
- 4 - F 09 OR2 0 3 0 1 :414
- 6 - F 03 OR2 s 0 4 0 1 ~480~1
- 5 - F 03 OR2 ! 0 4 0 4 :480
- 6 - F 09 OR2 0 4 0 1 :562
- 3 - F 09 OR2 0 3 0 1 :568
- 3 - F 02 OR2 s 0 2 0 1 ~629~1
- 8 - F 09 OR2 0 4 0 1 :672
- 5 - F 09 OR2 0 4 0 1 :678
- 6 - F 10 OR2 s 0 4 0 3 ~696~1
- 8 - F 10 OR2 s 0 4 0 1 ~753~1
- 2 - F 02 OR2 s 0 3 1 0 ~1095~1
- 1 - F 04 OR2 s 0 3 1 0 ~1095~2
- 1 - F 02 OR2 s 0 3 1 0 ~1095~3
- 4 - F 04 OR2 0 3 1 0 :1095
- 6 - F 02 OR2 s 0 3 1 0 ~1155~1
- 3 - F 04 OR2 s 0 3 1 0 ~1155~2
- 5 - F 04 OR2 s 0 3 1 0 ~1155~3
- 7 - F 04 OR2 0 3 1 0 :1155
- 8 - F 03 OR2 0 4 1 0 :1489
- 1 - F 03 OR2 0 4 1 0 :1514
- 2 - F 03 OR2 0 4 1 0 :1541
- 4 - F 03 OR2 0 4 1 0 :1568
- 5 - F 02 OR2 0 4 1 0 :1622
- 3 - F 03 OR2 0 4 1 0 :1649
- 8 - F 04 AND2 1 2 1 0 :1862
- 7 - F 02 OR2 1 3 1 0 :1935
- 4 - F 02 AND2 1 2 1 0 :2008
- 2 - F 04 OR2 1 3 1 0 :2081
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\jiaotongdeng\fuza01.rpt
fuza01
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 6/ 96( 6%) 13/ 48( 27%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\jiaotongdeng\fuza01.rpt
fuza01
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: h:\jiaotongdeng\fuza01.rpt
fuza01
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: h:\jiaotongdeng\fuza01.rpt
fuza01
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC1_F10, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = !count0 & _LC6_F10;
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC4_F10, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = !count0 & count1 & _LC6_F10
# count0 & !count1 & _LC6_F10;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC3_F10, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = !count1 & count2 & _LC6_F10
# !count0 & count2 & _LC6_F10
# count0 & count1 & !count2 & _LC6_F10;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC2_F10, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = count3 & !_LC5_F10 & !_LC6_F4 & !_LC7_F3
# !count3 & _LC5_F10 & !_LC7_F3
# !count3 & _LC5_F10 & _LC6_F4;
-- Node name is 'led7s0'
-- Equation name is 'led7s0', type is output
led7s0 = _LC3_F3;
-- Node name is 'led7s1'
-- Equation name is 'led7s1', type is output
led7s1 = _LC5_F2;
-- Node name is 'led7s2'
-- Equation name is 'led7s2', type is output
led7s2 = !_LC7_F3;
-- Node name is 'led7s3'
-- Equation name is 'led7s3', type is output
led7s3 = _LC4_F3;
-- Node name is 'led7s4'
-- Equation name is 'led7s4', type is output
led7s4 = _LC2_F3;
-- Node name is 'led7s5'
-- Equation name is 'led7s5', type is output
led7s5 = _LC1_F3;
-- Node name is 'led7s6'
-- Equation name is 'led7s6', type is output
led7s6 = _LC8_F3;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC4_F4;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC7_F4;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC8_F4;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC6_F2;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC2_F2;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC7_F2;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC1_F4;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC3_F4;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC4_F2;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC5_F4;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC1_F2;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC2_F4;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC7_F10, type is buried.
state0 = DFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = _LC3_F2 & _LC6_F4
# _LC5_F3 & _LC6_F4
# _LC8_F10;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC2_F9, type is buried.
state1 = DFFE( _EQ006, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = _LC5_F9 & !state0 & !state1
# _LC5_F9 & !state2;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC1_F9, type is buried.
state2 = DFFE( _EQ007, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = _LC8_F9 & !state2
# _LC8_F9 & !state0 & !state1;
-- Node name is '|LPM_ADD_SUB:330|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_F10', type is buried
_LC5_F10 = LCELL( _EQ008);
_EQ008 = count0 & count1 & count2;
-- Node name is '~353~1'
-- Equation name is '~353~1', location is LC6_F4, type is buried.
-- synthesized logic cell
!_LC6_F4 = _LC6_F4~NOT;
_LC6_F4~NOT = LCELL( _EQ009);
_EQ009 = !state0 & !state2;
-- Node name is ':363'
-- Equation name is '_LC7_F3', type is buried
!_LC7_F3 = _LC7_F3~NOT;
_LC7_F3~NOT = LCELL( _EQ010);
_EQ010 = count2
# !count1
# count3
# count0;
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