📄 fuza01.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
entity fuza01 is
port(clk,reset:in std_logic;
led7s:out std_logic_vector(6 downto 0);
pout:out std_logic_vector(12 downto 1));
end ;
architecture one of fuza01 is
signal er,ey,eg:std_logic;
signal sr,sy,sg:std_logic;
signal wr,wy,wg:std_logic;
signal nr,ny,ng:std_logic;
signal count:integer range 0 to 8;
signal state:integer range 0 to 4;
begin
process(clk,reset,count)
begin
if reset='1' then
count<=0;
state<=0;
else if(clk'event and clk='1')then
count<=count+1;
if(state=0 or state=2)then
if(count=2)then state<=state+1;count<=0;
end if;
else if(state=4 and count=2)then state<=1;count<=0;
else if(count>=8)then state<=state+1;
count<=0;
end if;end if;end if;
if(state>4)then state<=1;
end if;end if;end if;
case state is
when 0=>ey<='1';wy<='1';sy<='1';ny<='1';
eg<='0';wg<='0';sg<='0';ng<='0';
er<='0';wr<='0';sr<='0';nr<='0';
when 1=>ey<='0';wy<='0';sy<='0';ny<='0';
eg<='1';wg<='1';sg<='0';ng<='0';
er<='0';wr<='0';sr<='1';nr<='1';
when 2=>ey<='1';wy<='1';sy<='0';ny<='0';
eg<='1';wg<='1';sg<='0';ng<='0';
er<='0';wr<='0';sr<='1';nr<='1';
when 3=>ey<='0';wy<='0';sy<='0';ny<='0';
eg<='0';wg<='0';sg<='1';ng<='1';
er<='1';wr<='1';sr<='0';nr<='0';
when 4=>ey<='0';wy<='0';sy<='1';ny<='1';
eg<='0';wg<='0';sg<='1';ng<='1';
er<='1';wr<='1';sr<='0';nr<='0';
when others=>null;
end case;
end process;
PROCESS(count)
BEGIN
CASE count IS
WHEN 0=>LED7S<="0111111";
WHEN 1=>LED7S<="0000110";
WHEN 2=>LED7S<="1011011";
WHEN 3=>LED7S<="1001111";
WHEN 4=>LED7S<="1100110";
WHEN 5=>LED7S<="1101101";
WHEN 6=>LED7S<="1111101";
WHEN 7=>LED7S<="0000111";
WHEN 8=>LED7S<="1111111";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
pout(1)<=er; pout(2)<=eg; pout(3)<=ey and clk;
pout(4)<=sr; pout(5)<=sg; pout(6)<=sy and clk;
pout(7)<=wr; pout(8)<=wg; pout(9)<=wy and clk;
pout(10)<=nr; pout(11)<=ng; pout(12)<=ny and clk;
end;
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