signext32.v.bak

来自「是verilog做的简化mips32指令系统。 有些小问题」· BAK 代码 · 共 25 行

`timescale 100ns/1ns
module SignExt32(immediate,clk,Extend);
	input [15:0] immediate;
	input clk;
	output reg [31:0] Extend;
	output reg [31:0] offset;
	
	reg [31:0] temp;
	
	always @(posedge clk)
	begin
		if(immediate[15]==1'b1)
		begin
			temp[31: 0]={17'b0,immediate[14:0]};
			Extend = ~temp+1;//as mentioned in Ifetch32 , 
							//we needn't to time 4 now , we offer all radix complement
		end
		else
		begin
			Extend[31:0] = {16'b0,immediate[15:0]};
		end
	end
	
endmodule