prev_cmp_mips_top.tan.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register ALU32:alu\|s2\[2\] register ALU32:alu\|shifter32_var:myshift\|outreg\[17\] 95.27 MHz 10.496 ns Internal " "Info: Clock \"clock\" has Internal fmax of 95.27 MHz between source register \"ALU32:alu\|s2\[2\]\" and destination register \"ALU32:alu\|shifter32_var:myshift\|outreg\[17\]\" (period= 10.496 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.104 ns + Longest register register " "Info: + Longest register to register delay is 5.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ALU32:alu\|s2\[2\] 1 REG LCCOMB_X14_Y14_N10 38 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X14_Y14_N10; Fanout = 38; REG Node = 'ALU32:alu\|s2\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ALU32:alu|s2[2] } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.366 ns) 1.312 ns ALU32:alu\|shifter32_var:myshift\|outreg~14183 2 COMB LCCOMB_X15_Y17_N28 49 " "Info: 2: + IC(0.946 ns) + CELL(0.366 ns) = 1.312 ns; Loc. = LCCOMB_X15_Y17_N28; Fanout = 49; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14183'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { ALU32:alu|s2[2] ALU32:alu|shifter32_var:myshift|outreg~14183 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.053 ns) 2.413 ns ALU32:alu\|shifter32_var:myshift\|outreg~14265 3 COMB LCCOMB_X11_Y18_N26 2 " "Info: 3: + IC(1.048 ns) + CELL(0.053 ns) = 2.413 ns; Loc. = LCCOMB_X11_Y18_N26; Fanout = 2; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14265'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.101 ns" { ALU32:alu|shifter32_var:myshift|outreg~14183 ALU32:alu|shifter32_var:myshift|outreg~14265 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.366 ns) 3.449 ns ALU32:alu\|shifter32_var:myshift\|outreg~14644 4 COMB LCCOMB_X11_Y19_N12 1 " "Info: 4: + IC(0.670 ns) + CELL(0.366 ns) = 3.449 ns; Loc. = LCCOMB_X11_Y19_N12; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14644'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.036 ns" { ALU32:alu|shifter32_var:myshift|outreg~14265 ALU32:alu|shifter32_var:myshift|outreg~14644 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.228 ns) 4.515 ns ALU32:alu\|shifter32_var:myshift\|outreg~305 5 COMB LCCOMB_X9_Y18_N8 1 " "Info: 5: + IC(0.838 ns) + CELL(0.228 ns) = 4.515 ns; Loc. = LCCOMB_X9_Y18_N8; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~305'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.066 ns" { ALU32:alu|shifter32_var:myshift|outreg~14644 ALU32:alu|shifter32_var:myshift|outreg~305 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.209 ns) + CELL(0.225 ns) 4.949 ns ALU32:alu\|shifter32_var:myshift\|outreg~14658 6 COMB LCCOMB_X9_Y18_N26 1 " "Info: 6: + IC(0.209 ns) + CELL(0.225 ns) = 4.949 ns; Loc. = LCCOMB_X9_Y18_N26; Fanout = 1; COMB Node = 'ALU32:alu\|shifter32_var:myshift\|outreg~14658'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.434 ns" { ALU32:alu|shifter32_var:myshift|outreg~305 ALU32:alu|shifter32_var:myshift|outreg~14658 } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.104 ns ALU32:alu\|shifter32_var:myshift\|outreg\[17\] 7 REG LCFF_X9_Y18_N27 1 " "Info: 7: + IC(0.000 ns) + CELL(0.155 ns) = 5.104 ns; Loc. = LCFF_X9_Y18_N27; Fanout = 1; REG Node = 'ALU32:alu\|shifter32_var:myshift\|outreg\[17\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { ALU32:alu|shifter32_var:myshift|outreg~14658 ALU32:alu|shifter32_var:myshift|outreg[17] } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.393 ns ( 27.29 % ) " "Info: Total cell delay = 1.393 ns ( 27.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.711 ns ( 72.71 % ) " "Info: Total interconnect delay = 3.711 ns ( 72.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.104 ns" { ALU32:alu|s2[2] ALU32:alu|shifter32_var:myshift|outreg~14183 ALU32:alu|shifter32_var:myshift|outreg~14265 ALU32:alu|shifter32_var:myshift|outreg~14644 ALU32:alu|shifter32_var:myshift|outreg~305 ALU32:alu|shifter32_var:myshift|outreg~14658 ALU32:alu|shifter32_var:myshift|outreg[17] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.104 ns" { ALU32:alu|s2[2] {} ALU32:alu|shifter32_var:myshift|outreg~14183 {} ALU32:alu|shifter32_var:myshift|outreg~14265 {} ALU32:alu|shifter32_var:myshift|outreg~14644 {} ALU32:alu|shifter32_var:myshift|outreg~305 {} ALU32:alu|shifter32_var:myshift|outreg~14658 {} ALU32:alu|shifter32_var:myshift|outreg[17] {} } { 0.000ns 0.946ns 1.048ns 0.670ns 0.838ns 0.209ns 0.000ns } { 0.000ns 0.366ns 0.053ns 0.366ns 0.228ns 0.225ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.054 ns - Smallest " "Info: - Smallest clock skew is -0.054 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 7.870 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 7.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 6 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 6; CLK Node = 'clock'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.712 ns) 2.774 ns clock_gen:clocks\|aludecoderclk 2 REG LCFF_X18_Y11_N23 5 " "Info: 2: + IC(1.208 ns) + CELL(0.712 ns) = 2.774 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 5; REG Node = 'clock_gen:clocks\|aludecoderclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.920 ns" { clock clock_gen:clocks|aludecoderclk } "NODE_NAME" } } { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.712 ns) 4.460 ns ALUDecoder:aludecoder\|aluctrl\[2\] 3 REG LCFF_X10_Y13_N29 73 " "Info: 3: + IC(0.974 ns) + CELL(0.712 ns) = 4.460 ns; Loc. = LCFF_X10_Y13_N29; Fanout = 73; REG Node = 'ALUDecoder:aludecoder\|aluctrl\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.686 ns" { clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] } "NODE_NAME" } } { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.053 ns) 4.841 ns ALU32:alu\|shclk 4 COMB LCCOMB_X11_Y13_N6 2 " "Info: 4: + IC(0.328 ns) + CELL(0.053 ns) = 4.841 ns; Loc. = LCCOMB_X11_Y13_N6; Fanout = 2; COMB Node = 'ALU32:alu\|shclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.381 ns" { ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 6.592 ns ALU32:alu\|shclk~clkctrl 5 COMB CLKCTRL_G1 70 " "Info: 5: + IC(1.751 ns) + CELL(0.000 ns) = 6.592 ns; Loc. = CLKCTRL_G1; Fanout = 70; COMB Node = 'ALU32:alu\|shclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { ALU32:alu|shclk ALU32:alu|shclk~clkctrl } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(0.618 ns) 7.870 ns ALU32:alu\|shifter32_var:myshift\|outreg\[17\] 6 REG LCFF_X9_Y18_N27 1 " "Info: 6: + IC(0.660 ns) + CELL(0.618 ns) = 7.870 ns; Loc. = LCFF_X9_Y18_N27; Fanout = 1; REG Node = 'ALU32:alu\|shifter32_var:myshift\|outreg\[17\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[17] } "NODE_NAME" } } { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.949 ns ( 37.47 % ) " "Info: Total cell delay = 2.949 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns ( 62.53 % ) " "Info: Total interconnect delay = 4.921 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.870 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[17] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.870 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[2] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|shifter32_var:myshift|outreg[17] {} } { 0.000ns 0.000ns 1.208ns 0.974ns 0.328ns 1.751ns 0.660ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 7.924 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 7.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 6 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 6; CLK Node = 'clock'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.712 ns) 2.774 ns clock_gen:clocks\|aludecoderclk 2 REG LCFF_X18_Y11_N23 5 " "Info: 2: + IC(1.208 ns) + CELL(0.712 ns) = 2.774 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 5; REG Node = 'clock_gen:clocks\|aludecoderclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.920 ns" { clock clock_gen:clocks|aludecoderclk } "NODE_NAME" } } { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.712 ns) 4.460 ns ALUDecoder:aludecoder\|aluctrl\[1\] 3 REG LCFF_X10_Y13_N23 12 " "Info: 3: + IC(0.974 ns) + CELL(0.712 ns) = 4.460 ns; Loc. = LCFF_X10_Y13_N23; Fanout = 12; REG Node = 'ALUDecoder:aludecoder\|aluctrl\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.686 ns" { clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[1] } "NODE_NAME" } } { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.228 ns) 5.050 ns ALU32:alu\|shclk 4 COMB LCCOMB_X11_Y13_N6 2 " "Info: 4: + IC(0.362 ns) + CELL(0.228 ns) = 5.050 ns; Loc. = LCCOMB_X11_Y13_N6; Fanout = 2; COMB Node = 'ALU32:alu\|shclk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.590 ns" { ALUDecoder:aludecoder|aluctrl[1] ALU32:alu|shclk } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(0.000 ns) 6.801 ns ALU32:alu\|shclk~clkctrl 5 COMB CLKCTRL_G1 70 " "Info: 5: + IC(1.751 ns) + CELL(0.000 ns) = 6.801 ns; Loc. = CLKCTRL_G1; Fanout = 70; COMB Node = 'ALU32:alu\|shclk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { ALU32:alu|shclk ALU32:alu|shclk~clkctrl } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.225 ns) 7.924 ns ALU32:alu\|s2\[2\] 6 REG LCCOMB_X14_Y14_N10 38 " "Info: 6: + IC(0.898 ns) + CELL(0.225 ns) = 7.924 ns; Loc. = LCCOMB_X14_Y14_N10; Fanout = 38; REG Node = 'ALU32:alu\|s2\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { ALU32:alu|shclk~clkctrl ALU32:alu|s2[2] } "NODE_NAME" } } { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.731 ns ( 34.46 % ) " "Info: Total cell delay = 2.731 ns ( 34.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.193 ns ( 65.54 % ) " "Info: Total interconnect delay = 5.193 ns ( 65.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.924 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[1] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|s2[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.924 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[1] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|s2[2] {} } { 0.000ns 0.000ns 1.208ns 0.974ns 0.362ns 1.751ns 0.898ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.228ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.870 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[2] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|shifter32_var:myshift|outreg[17] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.870 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[2] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|shifter32_var:myshift|outreg[17] {} } { 0.000ns 0.000ns 1.208ns 0.974ns 0.328ns 1.751ns 0.660ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.053ns 0.000ns 0.618ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.924 ns" { clock clock_gen:clocks|aludecoderclk ALUDecoder:aludecoder|aluctrl[1] ALU32:alu|shclk ALU32:alu|shclk~clkctrl ALU32:alu|s2[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.924 ns" { clock {} clock~combout {} clock_gen:clocks|aludecoderclk {} ALUDecoder:aludecoder|aluctrl[1] {} ALU32:alu|shclk {} ALU32:alu|shclk~clkctrl {} ALU32:alu|s2[2] {} } { 0.000ns 0.000ns 1.208ns 0.974ns 0.362ns 1.751ns 0.898ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.228ns 0.000ns 0.225ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganiz