alu32.v

是verilog做的简化mips32指令系统。 有些小问题

`timescale 100ns/1ns
module ALU32(r1,r2,im,aluctrl,ALUSrc,cin,clk,zero,result,cout);
	input [31:0] r1,r2,im; //two register input ,one sign extend input;
	input [3:0] aluctrl; //OP control;
	input cin;
	input clk;
	input ALUSrc;	//chose the second input; 
	output reg zero;	
	output reg [31:0] result;
	output cout;
	
	reg [31:0] t1,t2;	
	reg [31:0] a1,a2,s1;
	wire [31:0] result_addtemp,result_shifttemp;
	wire c0,c32;
	reg signal;
	reg [4:0] s2;
	reg adclk;
	reg shclk;
   
	shifter32_var myshift(.inputa(s1),.shamt(s2),
	.ctrlsig(signal),.shclk(shclk),.outreg(result_shifttemp));

	add32 myadd(.a(a1),.b(a2),.cin(c0),.adclk(adclk),
	.sum(result_addtemp),.co(c32));
	
	assign cout = c32;
	assign c0=cin;
	always @(clk)
	begin
		shclk=0;
		adclk=0;
		t1 = r1; 

	   if(ALUSrc)
	   begin
	      t2 = im;
	   end
	   else
	   begin
	      t2 = r2;
	   end
	  
		case(aluctrl)
			4'b0000:result[31:0] = (t1[31:0] & t2[31:0]);//and,andi
			4'b0001:result[31:0] = (t1[31:0] | t2[31:0]);//or,ori
			4'b0010:begin
					a1=t1;
					a2=t2;
					//c0=0;
					result=result_addtemp;
					#1
					adclk=1;
					$monitor($time, " a=%d, b=%d, result=%d",a1,a2,result);
					end//add,load,store,addi
			4'b0011:result[31:0] = ~(t1[31:0] | t2[31:0]);//nor
			4'b0100:begin 
					a1=t1;
					a2=(~t2+1);
					zero = (result_addtemp[31:0] == 32'h00000000) ? 1'b1 : 1'b0;
					#1
					adclk=1;
					$monitor($time, " a=%d, b=%d, zero=%b",a1,t2,zero);
					end//beq,bne
			4'b0101:begin
					a1=t1;
					a2=(~t2+1);
					result[31:0] = (result_addtemp[31] == 1) ? 32'h00000001 : 32'h00000000;
					#1
					adclk=1;
					$monitor($time, " a=%d, b=%d, result=%d",a1,t2,result);
					end//slt,slti qqzzzz
			4'b0110:begin
					a1=t1;
					a2=(~t2+1);
					result=result_addtemp;
					#1
					adclk=1;
					$monitor($time, " a=%d, b=%d, result=%d, result=%b",a1,t2,result,result);
					end//sub
			4'b1000:begin
					s1=t1;
					s2=t2[10:6];
					signal=1'b1;
					result=result_shifttemp;
					#1
					shclk=1;
					$monitor($time, " a=%b, b=%d, result=%b",s1,s2,result);
					end//sll
			4'b1001:begin 
					s1=t1;
					s2=t2[10:6];
					signal=1'b0;
					result=result_shifttemp;
					#1
					shclk=1;
					$monitor($time, " a=%b, b=%d, result=%b",s1,s2,result);
					end//srl
			default:begin
					result[31:0] = 32'h00000000;
					//cout=1'b0;
					end
		endcase
	end
endmodule