registers32.v

是verilog做的简化mips32指令系统。 有些小问题

`timescale 100ns/1ns
module Registers32(instruction,reset,pc_inc,memdata,aluresult,rd,rw,rwdw,rwds,mtr,clk,Read1,Read2);

	input [31:0] instruction;
	input [31:0] pc_inc;			//pc + 4
	input [31:0] memdata;
	input [31:0] aluresult;			//data from aluresult or data ram
	input [1:0] rd;					//reg destination (instruction[20:16] or instruction[15:11] or $ra(31))
	input [1:0] rwdw;				//reg data write width [ high16 low16 low8 all ]
	input rw;						//reg write enable signal
	input rwds;						//reg data write source pc+4 or from mux{alu result , dram}
	input clk;
	input reset;
	input mtr;
	output reg [31:0] Read1;
	output reg [31:0] Read2;
	
	integer i;
	reg [31:0] datasrc;
	reg [31:0] Registers[31:0];
	reg [31:0] write_data;
	reg [4:0] WriteAddr;

	always @ (posedge clk)
	begin
		if(mtr=='b1) datasrc=memdata;
		else datasrc=aluresult;
		if(rd == 2'b01)
	      begin
	          WriteAddr[4:0]=instruction[20:16];
	      end
	   else if(rd == 2'b10)
	      begin
	          WriteAddr[4:0]=instruction[15:11];
         end
      else
         begin
             WriteAddr[4:0]=5'b11110; 
	      end			
		if(rwds == 1'b1)
		   begin
		       write_data[31:0]=pc_inc[31:0];
		   end
		else
		   begin
		       write_data[31:0]=datasrc[31:0];
		   end
		Read1[31:0]=Registers[instruction[25:21]];
		Read2[31:0]=Registers[instruction[20:16]];
	end
	
	always @ (negedge clk)
	begin
		if (reset==1)
		begin
			for (i=0;i<=31;i=i+1)
				Registers[i]=i;
		end	
		else if(rw)
		begin
			if ((rwdw[1]==1)&&(rwdw[0]==1))
				Registers[WriteAddr][31:16]=write_data[15:0];
			else if ((rwdw[1]==1)&&(rwdw[0]==0))
				Registers[WriteAddr][31:0]=write_data[31:0];
			else if ((rwdw[1]==0)&&(rwdw[0]==1))
				Registers[WriteAddr][15:0]=write_data[15:0];
			else if ((rwdw[1]==0)&&(rwdw[0]==0))
				Registers[WriteAddr][7:0]=write_data[7:0];
		end
	end
endmodule