ls160.vhd

来自「含有七人表决器」· VHDL 代码 · 共 43 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ls160 IS
      PORT( data:IN STD_LOGIC_VECTOR(3 downto 0);
      clk,ld,p,t,clr:IN STD_LOGIC;
      count:BUFFER STD_LOGIC_VECTOR(3 downto 0);
      tc: OUT STD_LOGIC);
END ls160;

ARCHITECTURE behavior OF ls160 IS
BEGIN
    tc<='1' when (count="1001" and p='1' and t='1' and ld='1' and clr='1') else '0';
    cale:
        process(clk,clr,p,t,ld)
   begin
        if(rising_edge(clk)) then
           if(clr='1') then
              if(ld='1') then
                  if(p='1') then
                      if(t='1') then
                          if(count="1001") then
                              count<="0000";
                           else 
                              count<=count+1;
                          end if;
                           else 
                              count<=count;
                          end if;
                           else 
                              count<=count;
                          end if;
                           else 
                              count<=data;
                          end if;
                           else 
                              count<="0000";
                          end if;
                          end if;
    end process cale;
END behavior;