adder14.vhd

来自「含有七人表决器」· VHDL 代码 · 共 17 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY adder14 IS
  PORT(OP1,OP2  :IN std_logic_vector(3 DOWNTO 0);
            ci  :IN bit;
         result :OUT std_logic_vector(4 DOWNTO 0));
END adder14;

ARCHITECTURE behave OF adder14 IS
SIGNAL halfadd   :std_logic_vector(4 downto 0);
BEGIN
   halfadd<=op1+op2;
result<=halfadd WHEN ci='0' ELSE halfadd+1;
END behave;