📄 bin.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 6/144( 4%) 7/ 72( 9%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\pldshiyan\bin\bin.rpt
bin
** EQUATIONS **
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
en : INPUT;
-- Node name is 'G0'
-- Equation name is 'G0', type is output
G0 = _LC4_C14;
-- Node name is 'G1'
-- Equation name is 'G1', type is output
G1 = _LC6_C12;
-- Node name is 'G2'
-- Equation name is 'G2', type is output
G2 = _LC1_C12;
-- Node name is 'G3'
-- Equation name is 'G3', type is output
G3 = _LC2_C12;
-- Node name is ':334'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ001);
_EQ001 = B0 & B1 & B2 & !B3;
-- Node name is ':346'
-- Equation name is '_LC3_C14', type is buried
!_LC3_C14 = _LC3_C14~NOT;
_LC3_C14~NOT = LCELL( _EQ002);
_EQ002 = !B1
# B0
# !B2
# B3;
-- Node name is ':358'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ003);
_EQ003 = !B0 & B1 & !_LC2_C1;
-- Node name is ':370'
-- Equation name is '_LC3_C1', type is buried
!_LC3_C1 = _LC3_C1~NOT;
_LC3_C1~NOT = LCELL( _EQ004);
_EQ004 = !B1
# !B0
# _LC2_C1;
-- Node name is '~382~1'
-- Equation name is '~382~1', location is LC2_C1, type is buried.
-- synthesized logic cell
!_LC2_C1 = _LC2_C1~NOT;
_LC2_C1~NOT = LCELL( _EQ005);
_EQ005 = !B2 & !B3;
-- Node name is ':382'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ006);
_EQ006 = B0 & !B1 & !_LC2_C1;
-- Node name is ':426'
-- Equation name is '_LC4_C1', type is buried
_LC4_C1 = LCELL( _EQ007);
_EQ007 = !B2
# !B3;
-- Node name is '~566~1'
-- Equation name is '~566~1', location is LC3_C12, type is buried.
-- synthesized logic cell
!_LC3_C12 = _LC3_C12~NOT;
_LC3_C12~NOT = LCELL( _EQ008);
_EQ008 = !B1 & B2 & !B3;
-- Node name is '~566~2'
-- Equation name is '~566~2', location is LC8_C12, type is buried.
-- synthesized logic cell
!_LC8_C12 = _LC8_C12~NOT;
_LC8_C12~NOT = LCELL( _EQ009);
_EQ009 = _LC3_C14
# _LC2_C14
# !_LC3_C12;
-- Node name is ':566'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ010);
_EQ010 = !_LC1_C1 & _LC1_C14 & !_LC3_C1 & _LC8_C12;
-- Node name is '~572~1'
-- Equation name is '~572~1', location is LC7_C12, type is buried.
-- synthesized logic cell
_LC7_C12 = LCELL( _EQ011);
_EQ011 = !_LC1_C1 & !_LC3_C1;
-- Node name is ':572'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ012);
_EQ012 = _LC1_C14 & _LC7_C12 & !_LC8_C12
# _LC1_C14 & _LC4_C1 & _LC7_C12;
-- Node name is '~578~1'
-- Equation name is '~578~1', location is LC6_C14, type is buried.
-- synthesized logic cell
_LC6_C14 = LCELL( _EQ013);
_EQ013 = B1 & en
# B0 & en
# en & _LC2_C1;
-- Node name is '~578~2'
-- Equation name is '~578~2', location is LC1_C14, type is buried.
-- synthesized logic cell
_LC1_C14 = LCELL( _EQ014);
_EQ014 = B1 & _LC6_C14
# !B0 & _LC6_C14
# _LC2_C1 & _LC6_C14;
-- Node name is '~578~3'
-- Equation name is '~578~3', location is LC4_C12, type is buried.
-- synthesized logic cell
_LC4_C12 = LCELL( _EQ015);
_EQ015 = !B3
# !B1 & !B2
# B1 & B2;
-- Node name is '~578~4'
-- Equation name is '~578~4', location is LC5_C12, type is buried.
-- synthesized logic cell
_LC5_C12 = LCELL( _EQ016);
_EQ016 = !_LC2_C14 & !_LC3_C12 & !_LC3_C14
# !_LC2_C14 & !_LC3_C14 & _LC4_C12;
-- Node name is ':578'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = LCELL( _EQ017);
_EQ017 = _LC1_C14 & _LC3_C1
# _LC1_C1 & _LC1_C14
# _LC1_C14 & _LC5_C12;
-- Node name is '~584~1'
-- Equation name is '~584~1', location is LC7_C14, type is buried.
-- synthesized logic cell
_LC7_C14 = LCELL( _EQ018);
_EQ018 = B0 & B1 & !B2
# !B0 & !B1 & !B2
# !B0 & B1 & B2
# B1 & !B3
# !B0 & !B3
# !B2 & !B3
# B0 & !B1 & B2 & B3;
-- Node name is '~584~2'
-- Equation name is '~584~2', location is LC8_C14, type is buried.
-- synthesized logic cell
_LC8_C14 = LCELL( _EQ019);
_EQ019 = _LC1_C1
# _LC2_C14 & !_LC3_C14
# !_LC3_C14 & _LC7_C14;
-- Node name is ':584'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ020);
_EQ020 = _LC5_C14 & _LC6_C14
# !_LC3_C1 & _LC6_C14 & _LC8_C14;
Project Information g:\pldshiyan\bin\bin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:38
Timing SNF Extractor 00:00:02
Assembler 00:00:18
-------------------------- --------
Total Time 00:01:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,906K
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