encoder.vhd

来自「含有七人表决器」· VHDL 代码 · 共 25 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY encoder IS
   PORT (e,f,g,h,i,j  :IN std_logic;
        codeout  :OUT std_logic_vector(3 DOWNTO 0)
      );
END encoder;
ARCHITECTURE behave OF encoder IS
   BEGIN
Codeout<="1111"WHEN j='1' ELSE
         "1110"WHEN i='1' ELSE
         "1101"WHEN h='1' ELSE
         "1100"WHEN g='1' ELSE
         "1011"WHEN f='1' ELSE
         "1010"WHEN e='1' ELSE
         
                 
         "0000";
END behave;