d.vhd

含有七人表决器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity D IS 
    PORT
        (
        D,CLK:  IN     std_logic;
        Q: OUT  std_logic
        );
END D;

ARCHITECTURE behave OF D IS
BEGIN
    PROCESS(CLK)
    BEGIN 
        IF(CLK'EVENT AND CLK='1')THEN
            Q<=D;
        END IF;
    END PROCESS;
END behave;

--JK触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY JK IS
    PORT
       (
       CLR,J,CLK,K,PSET:  IN  std_logic;   
       Q,QB: OUT std_logic
        );
END JK;
 
ARCHITECTURE behave OF JK IS
    SIGNAL Q_S,QB_S:STD_LOGIC;
BEGIN
    PROCESS(CLK,CLR,PSET,J,K)
    BEGIN
        IF (PSET='0')AND(CLR='1')THEN
           Q_S<='1';
           QB_S<='0';
        ELSIF  (PSET='1')AND(CLR='0')THEN
           Q_S<='0';
           QB_S<='1';
        ELSIF(CLK'EVENT AND CLK='1')THEN
               IF(J='0')AND(K='1')THEN
                   Q_S<='0';
                   QB_S<='1';
               ELSIF(J='1')AND(K='0')THEN
                   Q_S<='1';
                   QB_S<='0'; 
               ELSIF(J='1')AND(K='1')THEN
                   Q_S<=NOT Q_S;
                   QB_S<=NOT QB_S;
               END IF;
         END IF;
         Q<=Q_S;
         QB<=QB_S;
     END PROCESS;
END behave;