decode48.vhd

来自「含有七人表决器」· VHDL 代码 · 共 33 行

LIBRARY ieee
USE ieee.std_logic_1164.ALL;

ENTITY decode48 IS
  PORT(adr      :IN std_logic_vetor(3 DOWNTO 0);
       en       :IN std_logic_;
       decodeout        :OUT std_logic_vector(6 DOWNTO 0);
);
END decode48;

ARCHITECYURE archmux OF decode48 IS 
  BEGIN
   PORCESS(en,ard)
    BEGIN
     IF en='0' THEN
          decodeout<="0000000";
     EISE
      CASE ard IS
           WHEN "0000"=>decodeout<="1111110";
           WHEN "0001"=>decodeout<="0110000"; 
           WHEN "0010"=>decodeout<="1101101"; 
           WHEN "0011"=>decodeout<="1111001"; 
           WHEN "0100"=>decodeout<="0110011"; 
           WHEN "0101"=>decodeout<="1011011";
           WHEN "0110"=>decodeout<="1011111";
           WHEN "0111"=>decodeout<="1110000"; 
           WHEN "1000"=>decodeout<="1111111";
           WHEN OTHERS=>decodeout<="1111011";
     END CASE;
   END IF;
   END PROCESS;
END archmux