alpher2.vhd

来自「含有七人表决器」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alpher2 IS
PORT(clk :IN  STD_LOGIC;
    choice :OUT STD_LOGIC_VECTOR(7  downto  0);
        data  :OUT   STD_LOGIC_VECTOR(7  downto  0));
END alpher2;

ARCHITECTURE a OF alpher2 IS
    SIGNAL COUNT  : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL temp  : STD_LOGIC_VECTOR(3 downto 0);
BEGIN
    choice<="11111111";
        clk1_label:
        PROCESS (clk)
    BEGIN
        IF clk'event and clk='1' THEN                                     
            if count="1000" then  count<="0000";
            else  count<=count+1;
        end if;
    END IF;
END PROCESS clk1_label;
WITH count select
    data  <=
    "11101110" WHEN "0000",--A
    "00111110" WHEN "0001",--B
    "10011100" WHEN "0010",--C
    "01111010" WHEN "0011",--D
    "10011110" WHEN "0100",--E
    "10001110" WHEN "0101",--F
    "01101110" WHEN "0110",--H
    "11001110" WHEN "0111",--P
    "00011100" WHEN OTHERS;
END a;