prev_cmp_traffic.map.qmsg

Verilog HDL语言设计的交通灯设计

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "agreen\[5\] traffic.v(20) " "Info (10041): Inferred latch for \"agreen\[5\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "agreen\[6\] traffic.v(20) " "Info (10041): Inferred latch for \"agreen\[6\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "agreen\[7\] traffic.v(20) " "Info (10041): Inferred latch for \"agreen\[7\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[0\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[0\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[1\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[1\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[2\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[2\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[3\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[3\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[4\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[4\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[5\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[5\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[6\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[6\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ayellow\[7\] traffic.v(20) " "Info (10041): Inferred latch for \"ayellow\[7\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[0\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[0\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[1\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[1\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[2\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[2\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[3\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[3\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[4\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[4\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[5\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[5\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[6\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[6\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ared\[7\] traffic.v(20) " "Info (10041): Inferred latch for \"ared\[7\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|traffic\|countb 5 " "Info: State machine \"\|traffic\|countb\" contains 5 states" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|traffic\|counta 5 " "Info: State machine \"\|traffic\|counta\" contains 5 states" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|traffic\|countb " "Info: Selected Auto state machine encoding method for state machine \"\|traffic\|countb\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|traffic\|countb " "Info: Encoding result for state machine \"\|traffic\|countb\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "countb.011 " "Info: Encoded state bit \"countb.011\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "countb.010 " "Info: Encoded state bit \"countb.010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "countb.001 " "Info: Encoded state bit \"countb.001\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "countb.000 " "Info: Encoded state bit \"countb.000\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "countb.100 " "Info: Encoded state bit \"countb.100\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|countb.000 00000 " "Info: State \"\|traffic\|countb.000\" uses code string \"00000\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|countb.001 00110 " "Info: State \"\|traffic\|countb.001\" uses code string \"00110\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|countb.010 01010 " "Info: State \"\|traffic\|countb.010\" uses code string \"01010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|countb.011 10010 " "Info: State \"\|traffic\|countb.011\" uses code string \"10010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|countb.100 00011 " "Info: State \"\|traffic\|countb.100\" uses code string \"00011\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|traffic\|counta " "Info: Selected Auto state machine encoding method for state machine \"\|traffic\|counta\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|traffic\|counta " "Info: Encoding result for state machine \"\|traffic\|counta\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "counta.011 " "Info: Encoded state bit \"counta.011\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "counta.010 " "Info: Encoded state bit \"counta.010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "counta.001 " "Info: Encoded state bit \"counta.001\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "counta.000 " "Info: Encoded state bit \"counta.000\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "counta.100 " "Info: Encoded state bit \"counta.100\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|counta.000 00000 " "Info: State \"\|traffic\|counta.000\" uses code string \"00000\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|counta.001 00110 " "Info: State \"\|traffic\|counta.001\" uses code string \"00110\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|counta.010 01010 " "Info: State \"\|traffic\|counta.010\" uses code string \"01010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|counta.011 10010 " "Info: State \"\|traffic\|counta.011\" uses code string \"10010\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|counta.100 00011 " "Info: State \"\|traffic\|counta.100\" uses code string \"00011\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "counta.011 LAMPA\[0\]~reg0 " "Info: Duplicate register \"counta.011\" merged to single register \"LAMPA\[0\]~reg0\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "counta.001 LAMPA\[1\]~reg0 " "Info: Duplicate register \"counta.001\" merged to single register \"LAMPA\[1\]~reg0\"" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "counta.000 LAMPA\[3\]~reg0 " "Info: Duplicate register \"counta.000\" merged to single register \"LAMPA\[3\]~reg0\", power-up level changed" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 4 " "Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "countb~37 " "Info: Register \"countb~37\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "countb~38 " "Info: Register \"countb~38\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counta~37 " "Info: Register \"counta~37\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counta~38 " "Info: Register \"counta~38\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "93 " "Info: Implemented 93 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "67 " "Info: Implemented 67 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 30 23:21:17 2008 " "Info: Processing ended: Tue Dec 30 23:21:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}