prev_cmp_traffic.qmsg

Verilog HDL语言设计的交通灯设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 30 23:22:19 2008 " "Info: Processing started: Tue Dec 30 23:22:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Info: Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ared traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"ared\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ayellow traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"ayellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "agreen traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"agreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "aleft traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"aleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bred traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"bred\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "byellow traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"byellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bleft traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"bleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bgreen traffic.v(20) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(20): inferring latch(es) for variable \"bgreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(57) " "Warning (10230): Verilog HDL assignment warning at traffic.v(57): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(59) " "Warning (10230): Verilog HDL assignment warning at traffic.v(59): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(92) " "Warning (10230): Verilog HDL assignment warning at traffic.v(92): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 92 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(95) " "Warning (10230): Verilog HDL assignment warning at traffic.v(95): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[0\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[0\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[1\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[1\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[2\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[2\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[3\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[3\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[4\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[4\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[5\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[5\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[6\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[6\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[7\] traffic.v(20) " "Info (10041): Inferred latch for \"bgreen\[7\]\" at traffic.v(20)" {  } { { "traffic.v" "" { Text "E:/traffic/traffic.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}