traffic.sim.rpt

Verilog HDL语言设计的交通灯设计

; |traffic|countb.011           ; |traffic|countb.011           ; regout           ;
; |traffic|countb.001           ; |traffic|countb.001           ; regout           ;
; |traffic|countb.100           ; |traffic|countb.100           ; regout           ;
; |traffic|countb.010           ; |traffic|countb.010           ; regout           ;
; |traffic|LAMPB[2]~446         ; |traffic|LAMPB[2]~446         ; combout          ;
; |traffic|countb.000           ; |traffic|countb.000           ; regout           ;
; |traffic|Equal0~78            ; |traffic|Equal0~78            ; combout          ;
; |traffic|Equal1~93            ; |traffic|Equal1~93            ; combout          ;
; |traffic|numb[7]~3122         ; |traffic|numb[7]~3122         ; combout          ;
; |traffic|numa[1]~1549         ; |traffic|numa[1]~1549         ; combout          ;
; |traffic|numa[1]~1550         ; |traffic|numa[1]~1550         ; combout          ;
; |traffic|Add1~109             ; |traffic|Add1~109             ; combout          ;
; |traffic|numa[2]~1552         ; |traffic|numa[2]~1552         ; combout          ;
; |traffic|Add1~110             ; |traffic|Add1~110             ; combout          ;
; |traffic|numa[3]~1554         ; |traffic|numa[3]~1554         ; combout          ;
; |traffic|numb[7]~3123         ; |traffic|numb[7]~3123         ; combout          ;
; |traffic|numa[5]~1556         ; |traffic|numa[5]~1556         ; combout          ;
; |traffic|Add0~110             ; |traffic|Add0~110             ; combout          ;
; |traffic|Equal1~94            ; |traffic|Equal1~94            ; combout          ;
; |traffic|WideNor0~5           ; |traffic|WideNor0~5           ; combout          ;
; |traffic|Equal2~93            ; |traffic|Equal2~93            ; combout          ;
; |traffic|numb[7]~3124         ; |traffic|numb[7]~3124         ; combout          ;
; |traffic|numb[1]~3125         ; |traffic|numb[1]~3125         ; combout          ;
; |traffic|Add3~109             ; |traffic|Add3~109             ; combout          ;
; |traffic|numb[2]~3127         ; |traffic|numb[2]~3127         ; combout          ;
; |traffic|numb[7]~3130         ; |traffic|numb[7]~3130         ; combout          ;
; |traffic|numb[6]~3132         ; |traffic|numb[6]~3132         ; combout          ;
; |traffic|Equal2~94            ; |traffic|Equal2~94            ; combout          ;
; |traffic|Equal1~95            ; |traffic|Equal1~95            ; combout          ;
; |traffic|Equal2~95            ; |traffic|Equal2~95            ; combout          ;
; |traffic|Equal0~79            ; |traffic|Equal0~79            ; combout          ;
; |traffic|LessThan0~72         ; |traffic|LessThan0~72         ; combout          ;
; |traffic|WideNor0             ; |traffic|WideNor0             ; combout          ;
; |traffic|LessThan1~72         ; |traffic|LessThan1~72         ; combout          ;
; |traffic|numb[1]~3135         ; |traffic|numb[1]~3135         ; combout          ;
; |traffic|numb[3]~3136         ; |traffic|numb[3]~3136         ; combout          ;
; |traffic|numb[3]~3137         ; |traffic|numb[3]~3137         ; combout          ;
; |traffic|countb.001~_wirecell ; |traffic|countb.001~_wirecell ; combout          ;
; |traffic|LAMPA[0]             ; |traffic|LAMPA[0]             ; padio            ;
; |traffic|LAMPA[1]             ; |traffic|LAMPA[1]             ; padio            ;
; |traffic|LAMPA[2]             ; |traffic|LAMPA[2]             ; padio            ;
; |traffic|LAMPA[3]             ; |traffic|LAMPA[3]             ; padio            ;
; |traffic|LAMPB[0]             ; |traffic|LAMPB[0]             ; padio            ;
; |traffic|LAMPB[1]             ; |traffic|LAMPB[1]             ; padio            ;
; |traffic|LAMPB[2]             ; |traffic|LAMPB[2]             ; padio            ;
; |traffic|LAMPB[3]             ; |traffic|LAMPB[3]             ; padio            ;
; |traffic|ACOUNT[0]            ; |traffic|ACOUNT[0]            ; padio            ;
; |traffic|ACOUNT[1]            ; |traffic|ACOUNT[1]            ; padio            ;
; |traffic|ACOUNT[2]            ; |traffic|ACOUNT[2]            ; padio            ;
; |traffic|ACOUNT[3]            ; |traffic|ACOUNT[3]            ; padio            ;
; |traffic|ACOUNT[4]            ; |traffic|ACOUNT[4]            ; padio            ;
; |traffic|ACOUNT[5]            ; |traffic|ACOUNT[5]            ; padio            ;
; |traffic|BCOUNT[0]            ; |traffic|BCOUNT[0]            ; padio            ;
; |traffic|BCOUNT[1]            ; |traffic|BCOUNT[1]            ; padio            ;
; |traffic|BCOUNT[2]            ; |traffic|BCOUNT[2]            ; padio            ;
; |traffic|BCOUNT[3]            ; |traffic|BCOUNT[3]            ; padio            ;
; |traffic|BCOUNT[4]            ; |traffic|BCOUNT[4]            ; padio            ;
; |traffic|BCOUNT[5]            ; |traffic|BCOUNT[5]            ; padio            ;
; |traffic|BCOUNT[6]            ; |traffic|BCOUNT[6]            ; padio            ;
; |traffic|CLK                  ; |traffic|CLK~corein           ; combout          ;
+-------------------------------+-------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------+
; Missing 1-Value Coverage                                   ;
+--------------------+--------------------+------------------+
; Node Name          ; Output Port Name   ; Output Port Type ;
+--------------------+--------------------+------------------+
; |traffic|ACOUNT[6] ; |traffic|ACOUNT[6] ; padio            ;
; |traffic|ACOUNT[7] ; |traffic|ACOUNT[7] ; padio            ;
; |traffic|BCOUNT[7] ; |traffic|BCOUNT[7] ; padio            ;
; |traffic|EN        ; |traffic|EN~corein ; combout          ;
+--------------------+--------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------+
; Missing 0-Value Coverage                                   ;
+--------------------+--------------------+------------------+
; Node Name          ; Output Port Name   ; Output Port Type ;
+--------------------+--------------------+------------------+
; |traffic|ACOUNT[6] ; |traffic|ACOUNT[6] ; padio            ;
; |traffic|ACOUNT[7] ; |traffic|ACOUNT[7] ; padio            ;
; |traffic|BCOUNT[7] ; |traffic|BCOUNT[7] ; padio            ;
; |traffic|EN        ; |traffic|EN~corein ; combout          ;
+--------------------+--------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 23:23:04 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Using vector source file "E:/traffic/traffic.vwf"
Warning: Can't display state machine states -- register holding state machine bit "|traffic|counta.011" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|traffic|counta.001" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|traffic|counta.000" was synthesized away
Info: Inverted registers were found during simulation
    Info: Register: |traffic|LAMPA[3]~reg0
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      94.59 %
Info: Number of transitions in simulation is 2687
Info: Quartus II Simulator was successful. 0 errors, 3 warnings
    Info: Allocated 99 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 23:23:06 2008
    Info: Elapsed time: 00:00:02