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//************---------------------------------------------*******************/
// -------------------------------
// | Decoding context |
// -------------------------------
// *************************
// * 'current registers' *
// *************************
// --------------------- storing_ctx current registers ------------
store_hrz_size_cur MV_T10BITS MAP={dec_storing_hrz_size_cur.0..dec_storing_hrz_size_cur.9}
store_y_even_base_add_cur MV_REG_SIZE MAP={dec_storing_y_even_ptr_cur.0..dec_storing_y_even_ptr_cur.31}
store_y_odd_base_add_cur MV_REG_SIZE MAP={dec_storing_y_odd_ptr_cur.0..dec_storing_y_odd_ptr_cur.31}
store_c_even_base_add_cur MV_REG_SIZE MAP={dec_storing_c_even_ptr_cur.0..dec_storing_c_even_ptr_cur.31}
store_c_odd_base_add_cur MV_REG_SIZE MAP={dec_storing_c_odd_ptr_cur.0..dec_storing_c_odd_ptr_cur.31}
use_storing_bottom_cur MV_BIT MAP={dec_use_storing_cur.1}
use_storing_top_cur MV_BIT MAP={dec_use_storing_cur.0}
dec_frame_check_cur MV_BIT MAP={dec_storing_ctx_cur.4}
dec_picture_structure_cur MV_PICTURE_STRUCTURE MAP={dec_storing_ctx_cur.2..dec_storing_ctx_cur.3}
dec_tab_label_cur MV_TAB_LABEL MAP={dec_storing_ctx_cur.1}
dec_storing_format_cur MV_BIT MAP={dec_storing_ctx_cur.0}
// ----------------------- past_ctx current register ------------------------
past_y_odd_base_add_cur MV_REG_SIZE MAP={dec_past_y_odd_ptr_cur.0..dec_past_y_odd_ptr_cur.31}
past_y_even_base_add_cur MV_REG_SIZE MAP={dec_past_y_even_ptr_cur.0..dec_past_y_even_ptr_cur.31}
past_c_odd_base_add_cur MV_REG_SIZE MAP={dec_past_c_odd_ptr_cur.0..dec_past_c_odd_ptr_cur.31}
past_c_even_base_add_cur MV_REG_SIZE MAP={dec_past_c_even_ptr_cur.0..dec_past_c_even_ptr_cur.31}
// ------------------------- future_ctx current register --------------------
future_y_odd_base_add_cur MV_REG_SIZE MAP={dec_future_y_odd_ptr_cur.0..dec_future_y_odd_ptr_cur.31}
future_y_even_base_add_cur MV_REG_SIZE MAP={dec_future_y_even_ptr_cur.0..dec_future_y_even_ptr_cur.31}
future_c_odd_base_add_cur MV_REG_SIZE MAP={dec_future_c_odd_ptr_cur.0..dec_future_c_odd_ptr_cur.31}
future_c_even_base_add_cur MV_REG_SIZE MAP={dec_future_c_even_ptr_cur.0..dec_future_c_even_ptr_cur.31}
// ------------------------- recovery_ctx current register --------------------
recovery_y_odd_base_add_cur MV_REG_SIZE MAP={dec_recovery_y_odd_ptr_cur.0..dec_recovery_y_odd_ptr_cur.31}
recovery_y_even_base_add_cur MV_REG_SIZE MAP={dec_recovery_y_even_ptr_cur.0..dec_recovery_y_even_ptr_cur.31}
recovery_c_odd_base_add_cur MV_REG_SIZE MAP={dec_recovery_c_odd_ptr_cur.0..dec_recovery_c_odd_ptr_cur.31}
recovery_c_even_base_add_cur MV_REG_SIZE MAP={dec_recovery_c_even_ptr_cur.0..dec_recovery_c_even_ptr_cur.31}
// *************************
// * 'next registers' *
// *************************
// --------------------- storing_ctx next registers ------------
store_hrz_size_nxt MV_T10BITS MAP={dec_storing_hrz_size_nxt.0..dec_storing_hrz_size_nxt.9}
store_y_even_base_add_nxt MV_REG_SIZE MAP={dec_storing_y_even_ptr_nxt.0..dec_storing_y_even_ptr_nxt.31}
store_y_odd_base_add_nxt MV_REG_SIZE MAP={dec_storing_y_odd_ptr_nxt.0..dec_storing_y_odd_ptr_nxt.31}
store_c_even_base_add_nxt MV_REG_SIZE MAP={dec_storing_c_even_ptr_nxt.0..dec_storing_c_even_ptr_nxt.31}
store_c_odd_base_add_nxt MV_REG_SIZE MAP={dec_storing_c_odd_ptr_nxt.0..dec_storing_c_odd_ptr_nxt.31}
use_storing_bottom_nxt MV_BIT MAP={dec_use_storing_nxt.1}
use_storing_top_nxt MV_BIT MAP={dec_use_storing_nxt.0}
dec_frame_check_nxt MV_BIT MAP={dec_storing_ctx_nxt.4}
dec_picture_structure_nxt MV_PICTURE_STRUCTURE MAP={dec_storing_ctx_nxt.2..dec_storing_ctx_nxt.3}
dec_tab_label_nxt MV_TAB_LABEL MAP={dec_storing_ctx_nxt.1}
dec_storing_format_nxt MV_BIT MAP={dec_storing_ctx_nxt.0}
// ----------------------- past_ctx next registers ------------------------
past_y_odd_base_add_nxt MV_REG_SIZE MAP={dec_past_y_odd_ptr_nxt.0..dec_past_y_odd_ptr_nxt.31}
past_y_even_base_add_nxt MV_REG_SIZE MAP={dec_past_y_even_ptr_nxt.0..dec_past_y_even_ptr_nxt.31}
past_c_odd_base_add_nxt MV_REG_SIZE MAP={dec_past_c_odd_ptr_nxt.0..dec_past_c_odd_ptr_nxt.31}
past_c_even_base_add_nxt MV_REG_SIZE MAP={dec_past_c_even_ptr_nxt.0..dec_past_c_even_ptr_nxt.31}
// ------------------------- future_ctx next registers --------------------
future_y_odd_base_add_nxt MV_REG_SIZE MAP={dec_future_y_odd_ptr_nxt.0..dec_future_y_odd_ptr_nxt.31}
future_y_even_base_add_nxt MV_REG_SIZE MAP={dec_future_y_even_ptr_nxt.0..dec_future_y_even_ptr_nxt.31}
future_c_odd_base_add_nxt MV_REG_SIZE MAP={dec_future_c_odd_ptr_nxt.0..dec_future_c_odd_ptr_nxt.31}
future_c_even_base_add_nxt MV_REG_SIZE MAP={dec_future_c_even_ptr_nxt.0..dec_future_c_even_ptr_nxt.31}
// ------------------------- recovery_ctx next registers --------------------
recovery_y_odd_base_add_nxt MV_REG_SIZE MAP={dec_recovery_y_odd_ptr_nxt.0..dec_recovery_y_odd_ptr_nxt.31}
recovery_y_even_base_add_nxt MV_REG_SIZE MAP={dec_recovery_y_even_ptr_nxt.0..dec_recovery_y_even_ptr_nxt.31}
recovery_c_odd_base_add_nxt MV_REG_SIZE MAP={dec_recovery_c_odd_ptr_nxt.0..dec_recovery_c_odd_ptr_nxt.31}
recovery_c_even_base_add_nxt MV_REG_SIZE MAP={dec_recovery_c_even_ptr_nxt.0..dec_recovery_c_even_ptr_nxt.31}
// -------------------------------
// | Display context |
// -------------------------------
// *************************
// * 'current registers' *
// *************************
// ---------- disp_ctx current registers -----------------------------------
d_ctx_top_free_cur MV_TOP_FREE MAP={disp_ctx_cur.3}
d_ctx_bottom_free_cur MV_BOTTOM_FREE MAP={disp_ctx_cur.2}
d_ctx_tab_label_cur MV_TAB_LABEL MAP={disp_ctx_cur.1}
d_ctx_storing_format_cur MV_STORING_FORMAT MAP={disp_ctx_cur.0}
// *************************
// * 'next registers' *
// *************************
// ---------- disp_ctx next registers -----------------------------------
d_ctx_top_free_nxt MV_TOP_FREE MAP={disp_ctx_nxt.3}
d_ctx_bottom_free_nxt MV_BOTTOM_FREE MAP={disp_ctx_nxt.2}
d_ctx_tab_label_nxt MV_TAB_LABEL MAP={disp_ctx_nxt.1}
d_ctx_storing_format_nxt MV_STORING_FORMAT MAP={disp_ctx_nxt.0}
// -------------------------------
// | INFO |
// -------------------------------
// ----------------------- info_fbm_event ----------------------
fbm_event MV_FBM_EVENT MAP={fbm_event.0..fbm_event.5}
fbm_event_enable MV_FBM_EVENT MAP={fbm_event_enable.0..fbm_event_enable.5}
fbm_event_clear MV_FBM_EVENT MAP={fbm_event_clear.0..fbm_event_clear.5}
fbm_event_set MV_FBM_EVENT MAP={fbm_event_set.0..fbm_event_set.5}
// ----------------------- setup error concealment ----------------------
high_flaged_error_lock MV_BIT MAP={setup_error_concealment.6}
medium_flaged_error_lock MV_BIT MAP={setup_error_concealment.5}
low_flaged_error_lock MV_BIT MAP={setup_error_concealment.4}
vlc_coef_error_lock MV_BIT MAP={setup_error_concealment.3}
vlc_eob_miss_error_lock MV_BIT MAP={setup_error_concealment.2}
vlc_mb_error_lock MV_BIT MAP={setup_error_concealment.1}
vect_error_lock MV_BIT MAP={setup_error_concealment.0}
// ----------------------- info_lines_status --------------------------------
MBline_number_disp MV_T6BITS MAP={info_lines_status.8..info_lines_status.13}
MBline_number_decoded MV_T6BITS MAP={info_lines_status.0..info_lines_status.5}
// ----------------------- info_buffer_number ----------------------
buffer_number MV_BUFFER_NUMBER MAP={info_buffer_number.0..info_buffer_number.6}
// -------------------------------
// | CMD |
// -------------------------------
// ----------------------- cmd_fbm -----------------------------------------
fbm_cmd MV_FBM_CMD_ALL MAP={cmd_fbm.0..cmd_fbm.9}
//*********------------------------------------------------*******************/
//********| SYSTEM TIME BASE MANAGEMENT CONTROL REGISTER |******************/
//*********------------------------------------------------*******************/
//******************----------------------------------************************/
//*****************| VIDEO SYSTEM CONTROL REGISTERS |***********************/
//******************----------------------------------************************/
// ----------------------- video_status ------------------------------
video_int_status MV_VIDEO_INT_STATUS MAP={video_int_status.0..video_int_status.17}
video_int_enable MV_VIDEO_INT_STATUS MAP={video_int_enable.0..video_int_enable.17}
video_int_clear MV_VIDEO_INT_STATUS MAP={video_int_clear.0..video_int_clear.17}
video_int_set MV_VIDEO_INT_STATUS MAP={video_int_set.0..video_int_set.17}
dss_mode MV_BIT MAP={setup_system_format.2}
video_format_selection MV_DATA_FORMAT MAP={setup_system_format.0..setup_system_format.1}
video_fifo_disable MV_BIT MAP={setup_system.2}
video_synchronisation_mode MV_VIDEO_BUF_CTRL DTS_LOCKED MAP={setup_system.0..setup_system.1}
// ----------------------- cmd_video_reset --------------------------------------
video_decoder_reset MV_BIT MAP={cmd_video_reset.1}
mpeg_reset MV_BIT MAP={cmd_video_reset.0}
// ----------------------- cmd_video --------------------------------------
load_stcb MV_BIT MAP={cmd_video.4}
load_stca MV_BIT MAP={cmd_video.3}
load_dts MV_BIT MAP={cmd_video.2}
discard MV_BIT MAP={cmd_video.1}
synchronize MV_BIT MAP={cmd_video.0}
// ----------------------- bitstr_vbv_delay --------------------------------
vbv_delay MV_T16BITS MAP={bitstr_vbv_delay.0..bitstr_vbv_delay.15}
// ----------------------- bitstr_vbv_buffer_size --------------------------
vbv_buffer_size MV_T10BITS MAP={bitstr_vbv_buffer_size.0..bitstr_vbv_buffer_size.9}
// ----------------------- bitstr_video_bitrate ----------------------------
video_bitrate MV_T18BITS MAP={bitstr_video_bitrate.0..bitstr_video_bitrate.17}
//*****************------------------------------------***********************/
//****************| MEMORY MAPPING CONTROL REGISTERS |**********************/
//*****************------------------------------------***********************/
// ----------------------- fifo config -----------------------------------------
video_fifo_start MV_REG_SIZE MAP={video_fifo_start.0..video_fifo_start.31}
video_fifo_size MV_REG_SIZE MAP={video_fifo_size.0..video_fifo_size.31}
video_fifo_under MV_REG_SIZE MAP={video_fifo_under.0..video_fifo_under.31}
video_fifo_over MV_REG_SIZE MAP={video_fifo_over.0..video_fifo_over.31}
video_fifo_bfm_update MV_BIT MAP={cmd_video_fifo.0}
video_fifo_bfm_dec MV_BIT MAP={cmd_video_fifo.1}
video_fifo_rdpt_update MV_BIT MAP={cmd_video_fifo.2}
clear_video_fifo_bfm MV_BIT MAP={cmd_video_fifo.3}
start_still_fifo_read MV_BIT MAP={cmd_video_fifo.4}
video_fifo_nxt_value MV_REG_SIZE MAP={video_fifo_nxt_value.0..video_fifo_nxt_value.31}
video_fifo_rdpt_cur MV_REG_SIZE MAP={video_fifo_rdpt_cur.0..video_fifo_rdpt_cur.31}
video_fifo_bfmu_cur MV_REG_SIZE MAP={video_fifo_bfmu_cur.0..video_fifo_bfmu_cur.31}
video_fifo_bfmo_cur MV_REG_SIZE MAP={video_fifo_bfmo_cur.0..video_fifo_bfmo_cur.31}
still_fifo_start MV_REG_SIZE MAP={still_fifo_start.0..still_fifo_start.31}
still_fifo_size MV_REG_SIZE MAP={still_fifo_size.0..still_fifo_size.31}
setup_video_fifo MV_BIT MAP={setup_video_fifo.0}
// ------------------------ buffer number --------------------------------
setup_buffer_number MV_T6BITS MAP={setup_buffer_number.0..setup_buffer_number.5}
//*****************------------------------------------***********************/
//****************| VIDEO DECODING CONTROL REGISTERS |**********************/
//*****************------------------------------------***********************/
// -------------------------------
// | BITSTREAM information |
// -------------------------------
seq_hor_size MV_SEQ_HOR_SIZE MAP={bitstr_seq_hor_size.0..bitstr_seq_hor_size.11}
seq_ver_size MV_SEQ_VER_SIZE MAP={bitstr_seq_ver_size.0..bitstr_seq_ver_size.11}
centre_hor_offset MV_CENTRE_HOR_OFFSET MAP={bitstr_centre_hor_offset.0..bitstr_centre_hor_offset.15}
centre_ver_offset MV_CENTRE_VER_OFFSET MAP={bitstr_centre_ver_offset.0..bitstr_centre_ver_offset.13}
disp_hor_size MV_DISP_SIZE MAP={bitstr_disp_hor_size.0..bitstr_disp_hor_size.15}
disp_ver_size MV_DISP_SIZE MAP={bitstr_disp_ver_size.0..bitstr_disp_ver_size.15}
// ----------------------- bitstr_param ------------------------------------
constraint MV_BIT MAP={bitstr_param.30}
coding_type MV_PICTURE_CODING_TYPE MAP={bitstr_param.27..bitstr_param.29}
picture_structure MV_PICTURE_STRUCTURE MAP={bitstr_param.25..bitstr_param.26}
progressive_frame MV_BIT MAP={bitstr_param.24}
top_field_first MV_BIT MAP={bitstr_param.23}
repeat_first_field MV_BIT MAP={bitstr_param.22}
mpeg1_2 MV_BIT MAP={bitstr_param.21}
low_delay MV_BIT MAP={bitstr_param.20}
progressive_sequence MV_BIT MAP={bitstr_param.19}
closed_gop MV_BIT MAP={bitstr_param.18}
broken_link MV_BIT MAP={bitstr_param.17}
chroma_420_type MV_BIT MAP={bitstr_param.16}
frame_rate MV_FRAME_RATE MAP={bitstr_param.12..bitstr_param.15}
profile_level MV_PROFILE_LEVEL MAP={bitstr_param.4..bitstr_param.11}
aspect_ratio MV_ASPECT_RATIO MAP={bitstr_param.0..bitstr_param.3}
// ----------------------- bitstr_temporal_reference ----------------------
temporal_reference MV_TEMPORAL_REFERENCE MAP={bitstr_temporal_reference.0..bitstr_temporal_reference.7}
// ----------------------- info_header add ----------------------
sequence_header_address MV_T21BITS MAP={info_seq_header.0..info_seq_header.20}
userdata_sequence_address MV_T21BITS MAP={info_userdata_seq.0..info_userdata_seq.20}
gop_header_address MV_T21BITS MAP={info_gop_header.0..info_gop_header.20}
userdata_gop_address MV_T21BITS MAP={info_userdata_gop.0..info_userdata_gop.20}
picture_header_address MV_T21BITS MAP={info_pict_header.0..info_pict_header.20}
userdata_picture_address MV_T21BITS MAP={info_userdata_pict.0..info_userdata_pict.20}
slice_header_address MV_T21BITS MAP={info_slice_header.0..info_slice_header.20}
pes_header_1_address MV_T21BITS MAP={info_pes_header_1.0..info_pes_header_1.20}
pes_header_2_address MV_T21BITS MAP={info_pes_header_2.0..info_pes_header_2.20}
// ----------------------- dts / pts / stc ----------------------
video_pts MV_T24BITS MAP={info_last_video_pts.0..info_last_video_pts.23}
video_dts MV_T24BITS MAP={info_last_video_dts.0..info_last_video_dts.23}
system_event MV_SYSTEM_EVENT MAP={system_event.0..system_event.1}
system_event_enable MV_SYSTEM_EVENT MAP={system_event_enable.0..system_event_enable.1}
system_event_clear MV_SYSTEM_EVENT MAP={system_event_clear.0..system_event_clear.1}
system_event_set MV_SYSTEM_EVENT MAP={system_event_set.0..system_event_set.1}
video_time_stamp MV_T24BITS MAP={setup_video_time_stamp.0..setup_video_time_stamp.23}
video_time_stamp_offset MV_T16BITS MAP={setup_video_time_stamp_offset.0..setup_video_time_stamp_offset.15}
info_video_stca MV_T24BITS MAP={info_video_stca.0..info_video_stca.23}
info_video_stcb MV_T24BITS MAP={info_video_stcb.0..info_video_stcb.23}
setup_stc MV_T24BITS MAP={setup_video_stc.0..setup_video_stc.23}
stc_choice MV_BIT MAP={setup_video_stc_choice.0}
info_video_time_stamp MV_T24BITS MAP={info_video_time_stamp.0..info_video_time_stamp.23}
// ----------------------------- video_event ---------------------------------
video_event MV_VIDEO_EVENT MAP={video_event.0..video_event.10}
video_event_enable MV_VIDEO_EVENT MAP={video_event_enable.0..video_event_enable.10}
video_event_clear MV_VIDEO_EVENT MAP={video_event_clear.0..video_event_clear.10}
video_event_set MV_VIDEO_EVENT MAP={video_event_set.0..video_event_set.10}
// ----------------------------- error_event ---------------------------------
error_event MV_ERROR_EVENT MAP={error_event.0..error_event.18}
error_event_enable MV_ERROR_EVENT MAP={error_event_enable.0..error_event_enable.18}
error_event_clear MV_ERROR_EVENT MAP={error_event_clear.0..error_event_clear.18}
error_event_set MV_ERROR_EVENT MAP={error_event_set.0..error_event_set.18}
//**********************---------------------------***************************/
//*********************| LATEST ADDED |**************************/
//**********************---------------------------***************************/
video_powerdown MV_BIT MAP={video_powerdown.0}
video_module_id MV_REG_SIZE MAP={video_module_id.0..video_module_id.31}
END
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