code3.tan.qmsg

数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register input_coding\[7\] state.inlock 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"input_coding\[7\]\" and destination register \"state.inlock\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.829 ns + Longest register register " "Info: + Longest register to register delay is 1.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns input_coding\[7\] 1 REG LCFF_X64_Y19_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y19_N29; Fanout = 1; REG Node = 'input_coding\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { input_coding[7] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns Equal0~27 2 COMB LCCOMB_X64_Y19_N28 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X64_Y19_N28; Fanout = 1; COMB Node = 'Equal0~27'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { input_coding[7] Equal0~27 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.371 ns) 0.946 ns process0~109 3 COMB LCCOMB_X64_Y19_N18 1 " "Info: 3: + IC(0.252 ns) + CELL(0.371 ns) = 0.946 ns; Loc. = LCCOMB_X64_Y19_N18; Fanout = 1; COMB Node = 'process0~109'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { Equal0~27 process0~109 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 1.346 ns process0~0 4 COMB LCCOMB_X64_Y19_N0 2 " "Info: 4: + IC(0.250 ns) + CELL(0.150 ns) = 1.346 ns; Loc. = LCCOMB_X64_Y19_N0; Fanout = 2; COMB Node = 'process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { process0~109 process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.150 ns) 1.745 ns Selector2~59 5 COMB LCCOMB_X64_Y19_N24 1 " "Info: 5: + IC(0.249 ns) + CELL(0.150 ns) = 1.745 ns; Loc. = LCCOMB_X64_Y19_N24; Fanout = 1; COMB Node = 'Selector2~59'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { process0~0 Selector2~59 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.829 ns state.inlock 6 REG LCFF_X64_Y19_N25 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 1.829 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'state.inlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector2~59 state.inlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.078 ns ( 58.94 % ) " "Info: Total cell delay = 1.078 ns ( 58.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns ( 41.06 % ) " "Info: Total interconnect delay = 0.751 ns ( 41.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.829 ns" { input_coding[7] Equal0~27 process0~109 process0~0 Selector2~59 state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.829 ns" { input_coding[7] Equal0~27 process0~109 process0~0 Selector2~59 state.inlock } { 0.000ns 0.000ns 0.252ns 0.250ns 0.249ns 0.000ns } { 0.000ns 0.323ns 0.371ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.690 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns state.inlock 3 REG LCFF_X64_Y19_N25 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'state.inlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl state.inlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl state.inlock } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.690 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns input_coding\[7\] 3 REG LCFF_X64_Y19_N29 1 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N29; Fanout = 1; REG Node = 'input_coding\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl input_coding[7] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[7] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl state.inlock } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[7] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.829 ns" { input_coding[7] Equal0~27 process0~109 process0~0 Selector2~59 state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.829 ns" { input_coding[7] Equal0~27 process0~109 process0~0 Selector2~59 state.inlock } { 0.000ns 0.000ns 0.252ns 0.250ns 0.249ns 0.000ns } { 0.000ns 0.323ns 0.371ns 0.150ns 0.150ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl state.inlock } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[7] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.inlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { state.inlock } {  } {  } "" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "input_coding\[0\] enter clk 4.796 ns register " "Info: tsu for register \"input_coding\[0\]\" (data pin = \"enter\", clock pin = \"clk\") is 4.796 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.522 ns + Longest pin register " "Info: + Longest pin to register delay is 7.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns enter 1 PIN PIN_W26 4 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 4; PIN Node = 'enter'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enter } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.389 ns) + CELL(0.378 ns) 6.629 ns input_coding\[7\]~286 2 COMB LCCOMB_X64_Y19_N8 8 " "Info: 2: + IC(5.389 ns) + CELL(0.378 ns) = 6.629 ns; Loc. = LCCOMB_X64_Y19_N8; Fanout = 8; COMB Node = 'input_coding\[7\]~286'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.767 ns" { enter input_coding[7]~286 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.660 ns) 7.522 ns input_coding\[0\] 3 REG LCFF_X64_Y19_N15 1 " "Info: 3: + IC(0.233 ns) + CELL(0.660 ns) = 7.522 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 1; REG Node = 'input_coding\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { input_coding[7]~286 input_coding[0] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 25.26 % ) " "Info: Total cell delay = 1.900 ns ( 25.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.622 ns ( 74.74 % ) " "Info: Total interconnect delay = 5.622 ns ( 74.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.522 ns" { enter input_coding[7]~286 input_coding[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.522 ns" { enter enter~combout input_coding[7]~286 input_coding[0] } { 0.000ns 0.000ns 5.389ns 0.233ns } { 0.000ns 0.862ns 0.378ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.690 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns input_coding\[0\] 3 REG LCFF_X64_Y19_N15 1 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 1; REG Node = 'input_coding\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl input_coding[0] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[0] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.522 ns" { enter input_coding[7]~286 input_coding[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.522 ns" { enter enter~combout input_coding[7]~286 input_coding[0] } { 0.000ns 0.000ns 5.389ns 0.233ns } { 0.000ns 0.862ns 0.378ns 0.660ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[0] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk oright in_right 7.875 ns register " "Info: tco from clock \"clk\" to destination pin \"oright\" through register \"in_right\" is 7.875 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.690 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns in_right 3 REG LCFF_X63_Y19_N1 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X63_Y19_N1; Fanout = 2; REG Node = 'in_right'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl in_right } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl in_right } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl in_right } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.935 ns + Longest register pin " "Info: + Longest register to pin delay is 4.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns in_right 1 REG LCFF_X63_Y19_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y19_N1; Fanout = 2; REG Node = 'in_right'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_right } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.127 ns) + CELL(2.808 ns) 4.935 ns oright 2 PIN PIN_AE22 0 " "Info: 2: + IC(2.127 ns) + CELL(2.808 ns) = 4.935 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'oright'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.935 ns" { in_right oright } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.808 ns ( 56.90 % ) " "Info: Total cell delay = 2.808 ns ( 56.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.127 ns ( 43.10 % ) " "Info: Total interconnect delay = 2.127 ns ( 43.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.935 ns" { in_right oright } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.935 ns" { in_right oright } { 0.000ns 2.127ns } { 0.000ns 2.808ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl in_right } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl in_right } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.935 ns" { in_right oright } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.935 ns" { in_right oright } { 0.000ns 2.127ns } { 0.000ns 2.808ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "input_coding\[1\] coding\[1\] clk 1.357 ns register " "Info: th for register \"input_coding\[1\]\" (data pin = \"coding\[1\]\", clock pin = \"clk\") is 1.357 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.690 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns input_coding\[1\] 3 REG LCFF_X64_Y19_N27 1 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 1; REG Node = 'input_coding\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl input_coding[1] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[1] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.599 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns coding\[1\] 1 PIN PIN_N26 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 2; PIN Node = 'coding\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { coding[1] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.149 ns) 1.515 ns input_coding\[1\]~feeder 2 COMB LCCOMB_X64_Y19_N26 1 " "Info: 2: + IC(0.367 ns) + CELL(0.149 ns) = 1.515 ns; Loc. = LCCOMB_X64_Y19_N26; Fanout = 1; COMB Node = 'input_coding\[1\]~feeder'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.516 ns" { coding[1] input_coding[1]~feeder } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.599 ns input_coding\[1\] 3 REG LCFF_X64_Y19_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.599 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 1; REG Node = 'input_coding\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { input_coding[1]~feeder input_coding[1] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.232 ns ( 77.05 % ) " "Info: Total cell delay = 1.232 ns ( 77.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.367 ns ( 22.95 % ) " "Info: Total interconnect delay = 0.367 ns ( 22.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { coding[1] input_coding[1]~feeder input_coding[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.599 ns" { coding[1] coding[1]~combout input_coding[1]~feeder input_coding[1] } { 0.000ns 0.000ns 0.367ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clk clk~clkctrl input_coding[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clk clk~combout clk~clkctrl input_coding[1] } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { coding[1] input_coding[1]~feeder input_coding[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.599 ns" { coding[1] coding[1]~combout input_coding[1]~feeder input_coding[1] } { 0.000ns 0.000ns 0.367ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}