code3.map.rpt

数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时

+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; code3.vhd                        ; yes             ; User VHDL File  ; E:/gfy3/code3.vhd            ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 15    ;
;                                             ;       ;
; Total combinational functions               ; 15    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 9     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 4     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 13    ;
;     -- Dedicated logic registers            ; 13    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 15    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 13    ;
; Total fan-out                               ; 98    ;
; Average fan-out                             ; 2.28  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |code3                     ; 15 (15)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 15   ; 0            ; |code3              ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+----------------------------------------------------------------+
; State Machine - |code3|state                                   ;
+----------------+----------------+---------------+--------------+
; Name           ; state.changing ; state.outlock ; state.inlock ;
+----------------+----------------+---------------+--------------+
; state.inlock   ; 0              ; 0             ; 0            ;
; state.outlock  ; 0              ; 1             ; 1            ;
; state.changing ; 1              ; 0             ; 1            ;
+----------------+----------------+---------------+--------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 13    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 11    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; input_coding[0]                        ; 1       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Dec 19 20:18:30 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off code3 -c code3
Info: Found 2 design units, including 1 entities, in source file code3.vhd
    Info: Found design unit 1: code3-behave
    Info: Found entity 1: code3
Info: Elaborating entity "code3" for the top level hierarchy
Info: State machine "|code3|state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|code3|state"
Info: Encoding result for state machine "|code3|state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "state.changing"
        Info: Encoded state bit "state.outlock"
        Info: Encoded state bit "state.inlock"
    Info: State "|code3|state.inlock" uses code string "000"
    Info: State "|code3|state.outlock" uses code string "011"
    Info: State "|code3|state.changing" uses code string "101"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 37 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 2 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 157 megabytes of memory during processing
    Info: Processing ended: Fri Dec 19 20:18:33 2008
    Info: Elapsed time: 00:00:03