📄 code3.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity code3 is
port(clk : in std_logic;
close : in std_logic;--关锁(拨码开关)
--input : in std_logic;--输入密码
enter : in std_logic;--密码确认
modify : in std_logic;--修改密码
reset : in std_logic;--复位
coding : in std_logic_vector(7 downto 0);
oright : out std_logic;
wrong : out std_logic
);
end code3;
architecture behave of code3 is
type state_type is( inlock, outlock, changing);
signal state : state_type;
signal input_coding : std_logic_vector(7 downto 0);
signal in_right : std_logic;
signal in_wrong : std_logic;
begin
oright <= in_right;
wrong <= in_wrong;
process(clk,coding,reset,close,enter,state)
begin
if(reset='0') then
input_coding <= "00000001";
state <= inlock;
elsif(clk'event and clk='1') then
case state is
when inlock =>
in_wrong<='1';
in_right<='0';
if(enter = '0' and coding = input_coding) then
state<=outlock;
else
state<=inlock;
end if;
when outlock =>
in_right <= '1';
in_wrong <= '0';
if(close='0') then
state<=inlock;
elsif (modify = '0') then
state <= changing;
else
state <= outlock;
end if;
when changing =>
if(enter='0') then
input_coding <= coding;
state <= outlock;
else
state <= changing;
end if;
end case;
end if;
end process;
end behave;
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