prev_cmp_code3.qmsg

数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时

{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Allocated 190 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 19 20:12:53 2008 " "Info: Processing ended: Fri Dec 19 20:12:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 19 20:12:54 2008 " "Info: Processing started: Fri Dec 19 20:12:54 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off code3 -c code3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off code3 -c code3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register input_coding\[6\] state.outlock 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"input_coding\[6\]\" and destination register \"state.outlock\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.032 ns + Longest register register " "Info: + Longest register to register delay is 2.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns input_coding\[6\] 1 REG LCFF_X61_Y2_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y2_N17; Fanout = 1; REG Node = 'input_coding\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { input_coding[6] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.275 ns) 0.593 ns process0~108 2 COMB LCCOMB_X61_Y2_N4 1 " "Info: 2: + IC(0.318 ns) + CELL(0.275 ns) = 0.593 ns; Loc. = LCCOMB_X61_Y2_N4; Fanout = 1; COMB Node = 'process0~108'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.593 ns" { input_coding[6] process0~108 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.275 ns) 1.119 ns process0~109 3 COMB LCCOMB_X61_Y2_N2 1 " "Info: 3: + IC(0.251 ns) + CELL(0.275 ns) = 1.119 ns; Loc. = LCCOMB_X61_Y2_N2; Fanout = 1; COMB Node = 'process0~109'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.526 ns" { process0~108 process0~109 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.150 ns) 1.521 ns process0~0 4 COMB LCCOMB_X61_Y2_N10 2 " "Info: 4: + IC(0.252 ns) + CELL(0.150 ns) = 1.521 ns; Loc. = LCCOMB_X61_Y2_N10; Fanout = 2; COMB Node = 'process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.402 ns" { process0~109 process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.150 ns) 1.948 ns Selector3~50 5 COMB LCCOMB_X61_Y2_N18 1 " "Info: 5: + IC(0.277 ns) + CELL(0.150 ns) = 1.948 ns; Loc. = LCCOMB_X61_Y2_N18; Fanout = 1; COMB Node = 'Selector3~50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.427 ns" { process0~0 Selector3~50 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.032 ns state.outlock 6 REG LCFF_X61_Y2_N19 4 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.032 ns; Loc. = LCFF_X61_Y2_N19; Fanout = 4; REG Node = 'state.outlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector3~50 state.outlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.934 ns ( 45.96 % ) " "Info: Total cell delay = 0.934 ns ( 45.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.098 ns ( 54.04 % ) " "Info: Total interconnect delay = 1.098 ns ( 54.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { input_coding[6] process0~108 process0~109 process0~0 Selector3~50 state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.032 ns" { input_coding[6] process0~108 process0~109 process0~0 Selector3~50 state.outlock } { 0.000ns 0.318ns 0.251ns 0.252ns 0.277ns 0.000ns } { 0.000ns 0.275ns 0.275ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.701 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 2.701 ns state.outlock 3 REG LCFF_X61_Y2_N19 4 " "Info: 3: + IC(1.047 ns) + CELL(0.537 ns) = 2.701 ns; Loc. = LCFF_X61_Y2_N19; Fanout = 4; REG Node = 'state.outlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl state.outlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.87 % ) " "Info: Total cell delay = 1.536 ns ( 56.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 43.13 % ) " "Info: Total interconnect delay = 1.165 ns ( 43.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl state.outlock } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.701 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 2.701 ns input_coding\[6\] 3 REG LCFF_X61_Y2_N17 1 " "Info: 3: + IC(1.047 ns) + CELL(0.537 ns) = 2.701 ns; Loc. = LCFF_X61_Y2_N17; Fanout = 1; REG Node = 'input_coding\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl input_coding[6] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.87 % ) " "Info: Total cell delay = 1.536 ns ( 56.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 43.13 % ) " "Info: Total interconnect delay = 1.165 ns ( 43.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl input_coding[6] } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl state.outlock } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl input_coding[6] } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { input_coding[6] process0~108 process0~109 process0~0 Selector3~50 state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.032 ns" { input_coding[6] process0~108 process0~109 process0~0 Selector3~50 state.outlock } { 0.000ns 0.318ns 0.251ns 0.252ns 0.277ns 0.000ns } { 0.000ns 0.275ns 0.275ns 0.150ns 0.150ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl state.outlock } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl input_coding[6] } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { state.outlock } {  } {  } "" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "state.outlock close clk 6.016 ns register " "Info: tsu for register \"state.outlock\" (data pin = \"close\", clock pin = \"clk\") is 6.016 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.753 ns + Longest pin register " "Info: + Longest pin to register delay is 8.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns close 1 PIN PIN_G26 2 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 2; PIN Node = 'close'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { close } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.319 ns) + CELL(0.413 ns) 7.594 ns Selector4~9 2 COMB LCCOMB_X61_Y2_N30 2 " "Info: 2: + IC(6.319 ns) + CELL(0.413 ns) = 7.594 ns; Loc. = LCCOMB_X61_Y2_N30; Fanout = 2; COMB Node = 'Selector4~9'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.732 ns" { close Selector4~9 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 7.994 ns Selector3~49 3 COMB LCCOMB_X61_Y2_N22 1 " "Info: 3: + IC(0.250 ns) + CELL(0.150 ns) = 7.994 ns; Loc. = LCCOMB_X61_Y2_N22; Fanout = 1; COMB Node = 'Selector3~49'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { Selector4~9 Selector3~49 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.420 ns) 8.669 ns Selector3~50 4 COMB LCCOMB_X61_Y2_N18 1 " "Info: 4: + IC(0.255 ns) + CELL(0.420 ns) = 8.669 ns; Loc. = LCCOMB_X61_Y2_N18; Fanout = 1; COMB Node = 'Selector3~50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { Selector3~49 Selector3~50 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.753 ns state.outlock 5 REG LCFF_X61_Y2_N19 4 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 8.753 ns; Loc. = LCFF_X61_Y2_N19; Fanout = 4; REG Node = 'state.outlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector3~50 state.outlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 22.04 % ) " "Info: Total cell delay = 1.929 ns ( 22.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.824 ns ( 77.96 % ) " "Info: Total interconnect delay = 6.824 ns ( 77.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.753 ns" { close Selector4~9 Selector3~49 Selector3~50 state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.753 ns" { close close~combout Selector4~9 Selector3~49 Selector3~50 state.outlock } { 0.000ns 0.000ns 6.319ns 0.250ns 0.255ns 0.000ns } { 0.000ns 0.862ns 0.413ns 0.150ns 0.420ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.701 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 2.701 ns state.outlock 3 REG LCFF_X61_Y2_N19 4 " "Info: 3: + IC(1.047 ns) + CELL(0.537 ns) = 2.701 ns; Loc. = LCFF_X61_Y2_N19; Fanout = 4; REG Node = 'state.outlock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl state.outlock } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.87 % ) " "Info: Total cell delay = 1.536 ns ( 56.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 43.13 % ) " "Info: Total interconnect delay = 1.165 ns ( 43.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl state.outlock } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.753 ns" { close Selector4~9 Selector3~49 Selector3~50 state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.753 ns" { close close~combout Selector4~9 Selector3~49 Selector3~50 state.outlock } { 0.000ns 0.000ns 6.319ns 0.250ns 0.255ns 0.000ns } { 0.000ns 0.862ns 0.413ns 0.150ns 0.420ns 0.084ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl state.outlock } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl state.outlock } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk oright in_right 6.628 ns register " "Info: tco from clock \"clk\" to destination pin \"oright\" through register \"in_right\" is 6.628 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.701 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 2.701 ns in_right 3 REG LCFF_X62_Y2_N7 2 " "Info: 3: + IC(1.047 ns) + CELL(0.537 ns) = 2.701 ns; Loc. = LCFF_X62_Y2_N7; Fanout = 2; REG Node = 'in_right'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl in_right } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.87 % ) " "Info: Total cell delay = 1.536 ns ( 56.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 43.13 % ) " "Info: Total interconnect delay = 1.165 ns ( 43.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl in_right } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl in_right } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.677 ns + Longest register pin " "Info: + Longest register to pin delay is 3.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns in_right 1 REG LCFF_X62_Y2_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y2_N7; Fanout = 2; REG Node = 'in_right'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_right } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.869 ns) + CELL(2.808 ns) 3.677 ns oright 2 PIN PIN_AE22 0 " "Info: 2: + IC(0.869 ns) + CELL(2.808 ns) = 3.677 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'oright'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.677 ns" { in_right oright } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.808 ns ( 76.37 % ) " "Info: Total cell delay = 2.808 ns ( 76.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.869 ns ( 23.63 % ) " "Info: Total interconnect delay = 0.869 ns ( 23.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.677 ns" { in_right oright } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.677 ns" { in_right oright } { 0.000ns 0.869ns } { 0.000ns 2.808ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl in_right } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl in_right } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.677 ns" { in_right oright } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.677 ns" { in_right oright } { 0.000ns 0.869ns } { 0.000ns 2.808ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "input_coding\[6\] coding\[6\] clk 0.148 ns register " "Info: th for register \"input_coding\[6\]\" (data pin = \"coding\[6\]\", clock pin = \"clk\") is 0.148 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.701 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 2.701 ns input_coding\[6\] 3 REG LCFF_X61_Y2_N17 1 " "Info: 3: + IC(1.047 ns) + CELL(0.537 ns) = 2.701 ns; Loc. = LCFF_X61_Y2_N17; Fanout = 1; REG Node = 'input_coding\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl input_coding[6] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.87 % ) " "Info: Total cell delay = 1.536 ns ( 56.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 43.13 % ) " "Info: Total interconnect delay = 1.165 ns ( 43.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl input_coding[6] } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.819 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns coding\[6\] 1 PIN PIN_AC13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AC13; Fanout = 2; PIN Node = 'coding\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { coding[6] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.596 ns) + CELL(0.150 ns) 2.735 ns input_coding~423 2 COMB LCCOMB_X61_Y2_N16 1 " "Info: 2: + IC(1.596 ns) + CELL(0.150 ns) = 2.735 ns; Loc. = LCCOMB_X61_Y2_N16; Fanout = 1; COMB Node = 'input_coding~423'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.746 ns" { coding[6] input_coding~423 } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.819 ns input_coding\[6\] 3 REG LCFF_X61_Y2_N17 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.819 ns; Loc. = LCFF_X61_Y2_N17; Fanout = 1; REG Node = 'input_coding\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { input_coding~423 input_coding[6] } "NODE_NAME" } } { "code3.vhd" "" { Text "E:/gfy3/code3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.223 ns ( 43.38 % ) " "Info: Total cell delay = 1.223 ns ( 43.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.596 ns ( 56.62 % ) " "Info: Total interconnect delay = 1.596 ns ( 56.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { coding[6] input_coding~423 input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { coding[6] coding[6]~combout input_coding~423 input_coding[6] } { 0.000ns 0.000ns 1.596ns 0.000ns } { 0.000ns 0.989ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { clk clk~clkctrl input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.701 ns" { clk clk~combout clk~clkctrl input_coding[6] } { 0.000ns 0.000ns 0.118ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { coding[6] input_coding~423 input_coding[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { coding[6] coding[6]~combout input_coding~423 input_coding[6] } { 0.000ns 0.000ns 1.596ns 0.000ns } { 0.000ns 0.989ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 19 20:12:55 2008 " "Info: Processing ended: Fri Dec 19 20:12:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}