code3.tan.rpt

数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时

; N/A           ; None        ; -1.857 ns ; coding[4] ; state.inlock    ; clk      ;
; N/A           ; None        ; -2.377 ns ; coding[7] ; state.outlock   ; clk      ;
; N/A           ; None        ; -2.380 ns ; coding[7] ; state.inlock    ; clk      ;
; N/A           ; None        ; -3.213 ns ; modify    ; state.changing  ; clk      ;
; N/A           ; None        ; -3.516 ns ; reset     ; in_right        ; clk      ;
; N/A           ; None        ; -3.516 ns ; reset     ; in_wrong        ; clk      ;
; N/A           ; None        ; -3.523 ns ; close     ; state.inlock    ; clk      ;
; N/A           ; None        ; -3.787 ns ; close     ; state.changing  ; clk      ;
; N/A           ; None        ; -3.792 ns ; enter     ; state.changing  ; clk      ;
; N/A           ; None        ; -3.922 ns ; modify    ; state.outlock   ; clk      ;
; N/A           ; None        ; -4.445 ns ; enter     ; state.outlock   ; clk      ;
; N/A           ; None        ; -4.448 ns ; enter     ; state.inlock    ; clk      ;
; N/A           ; None        ; -4.497 ns ; close     ; state.outlock   ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[0] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[3] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[2] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[1] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[5] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[7] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[4] ; clk      ;
; N/A           ; None        ; -4.566 ns ; enter     ; input_coding[6] ; clk      ;
+---------------+-------------+-----------+-----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Dec 19 20:19:07 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off code3 -c code3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "input_coding[7]" and destination register "state.inlock"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.829 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y19_N29; Fanout = 1; REG Node = 'input_coding[7]'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X64_Y19_N28; Fanout = 1; COMB Node = 'Equal0~27'
            Info: 3: + IC(0.252 ns) + CELL(0.371 ns) = 0.946 ns; Loc. = LCCOMB_X64_Y19_N18; Fanout = 1; COMB Node = 'process0~109'
            Info: 4: + IC(0.250 ns) + CELL(0.150 ns) = 1.346 ns; Loc. = LCCOMB_X64_Y19_N0; Fanout = 2; COMB Node = 'process0~0'
            Info: 5: + IC(0.249 ns) + CELL(0.150 ns) = 1.745 ns; Loc. = LCCOMB_X64_Y19_N24; Fanout = 1; COMB Node = 'Selector2~59'
            Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 1.829 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'state.inlock'
            Info: Total cell delay = 1.078 ns ( 58.94 % )
            Info: Total interconnect delay = 0.751 ns ( 41.06 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.690 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'state.inlock'
                Info: Total cell delay = 1.536 ns ( 57.10 % )
                Info: Total interconnect delay = 1.154 ns ( 42.90 % )
            Info: - Longest clock path from clock "clk" to source register is 2.690 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N29; Fanout = 1; REG Node = 'input_coding[7]'
                Info: Total cell delay = 1.536 ns ( 57.10 % )
                Info: Total interconnect delay = 1.154 ns ( 42.90 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "input_coding[0]" (data pin = "enter", clock pin = "clk") is 4.796 ns
    Info: + Longest pin to register delay is 7.522 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 4; PIN Node = 'enter'
        Info: 2: + IC(5.389 ns) + CELL(0.378 ns) = 6.629 ns; Loc. = LCCOMB_X64_Y19_N8; Fanout = 8; COMB Node = 'input_coding[7]~286'
        Info: 3: + IC(0.233 ns) + CELL(0.660 ns) = 7.522 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 1; REG Node = 'input_coding[0]'
        Info: Total cell delay = 1.900 ns ( 25.26 % )
        Info: Total interconnect delay = 5.622 ns ( 74.74 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 1; REG Node = 'input_coding[0]'
        Info: Total cell delay = 1.536 ns ( 57.10 % )
        Info: Total interconnect delay = 1.154 ns ( 42.90 % )
Info: tco from clock "clk" to destination pin "oright" through register "in_right" is 7.875 ns
    Info: + Longest clock path from clock "clk" to source register is 2.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X63_Y19_N1; Fanout = 2; REG Node = 'in_right'
        Info: Total cell delay = 1.536 ns ( 57.10 % )
        Info: Total interconnect delay = 1.154 ns ( 42.90 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.935 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y19_N1; Fanout = 2; REG Node = 'in_right'
        Info: 2: + IC(2.127 ns) + CELL(2.808 ns) = 4.935 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'oright'
        Info: Total cell delay = 2.808 ns ( 56.90 % )
        Info: Total interconnect delay = 2.127 ns ( 43.10 % )
Info: th for register "input_coding[1]" (data pin = "coding[1]", clock pin = "clk") is 1.357 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 1; REG Node = 'input_coding[1]'
        Info: Total cell delay = 1.536 ns ( 57.10 % )
        Info: Total interconnect delay = 1.154 ns ( 42.90 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 1.599 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 2; PIN Node = 'coding[1]'
        Info: 2: + IC(0.367 ns) + CELL(0.149 ns) = 1.515 ns; Loc. = LCCOMB_X64_Y19_N26; Fanout = 1; COMB Node = 'input_coding[1]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.599 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 1; REG Node = 'input_coding[1]'
        Info: Total cell delay = 1.232 ns ( 77.05 % )
        Info: Total interconnect delay = 0.367 ns ( 22.95 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Fri Dec 19 20:19:09 2008
    Info: Elapsed time: 00:00:02