decoder_time_post.vhd

8b10b design reference

    )
    port map (
      I => gout_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => gout_MC_Q
    );
  gout_MC_D1_107 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => gout_MC_D1
    );
  gout_MC_D2_PT_0_108 : X_AND2
    port map (
      I0 => NlwInverterSignal_gout_MC_D2_PT_0_IN0,
      I1 => gout,
      O => gout_MC_D2_PT_0
    );
  gout_MC_D2_PT_1_109 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => jin,
      I5 => NlwInverterSignal_gout_MC_D2_PT_1_IN5,
      O => gout_MC_D2_PT_1
    );
  gout_MC_D2_PT_2_110 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_gout_MC_D2_PT_2_IN3,
      I4 => NlwInverterSignal_gout_MC_D2_PT_2_IN4,
      I5 => fin,
      O => gout_MC_D2_PT_2
    );
  gout_MC_D2_PT_3_111 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => jin,
      I4 => NlwInverterSignal_gout_MC_D2_PT_3_IN4,
      I5 => NlwInverterSignal_gout_MC_D2_PT_3_IN5,
      O => gout_MC_D2_PT_3
    );
  gout_MC_D2_PT_4_112 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_gout_MC_D2_PT_4_IN3,
      I4 => N_PZ_88,
      I5 => fin,
      O => gout_MC_D2_PT_4
    );
  gout_MC_D2_PT_5_113 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => NlwInverterSignal_gout_MC_D2_PT_5_IN4,
      I5 => NlwInverterSignal_gout_MC_D2_PT_5_IN5,
      I6 => gin,
      O => gout_MC_D2_PT_5
    );
  gout_MC_D2_PT_6_114 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_gout_MC_D2_PT_6_IN3,
      I4 => jin,
      I5 => N_PZ_88,
      I6 => NlwInverterSignal_gout_MC_D2_PT_6_IN6,
      O => gout_MC_D2_PT_6
    );
  gout_MC_D2_115 : X_OR7
    port map (
      I0 => gout_MC_D2_PT_0,
      I1 => gout_MC_D2_PT_1,
      I2 => gout_MC_D2_PT_2,
      I3 => gout_MC_D2_PT_3,
      I4 => gout_MC_D2_PT_4,
      I5 => gout_MC_D2_PT_5,
      I6 => gout_MC_D2_PT_6,
      O => gout_MC_D2
    );
  gout_MC_XOR : X_XOR2
    port map (
      I0 => gout_MC_D1,
      I1 => gout_MC_D2,
      O => gout_MC_D
    );
  data_out_2_Q : X_BUF
    port map (
      I => data_out_2_MC_Q,
      O => data_out(2)
    );
  data_out_2_MC_Q_116 : X_BUF
    port map (
      I => data_out_2_MC_Q_tsim_ireg_Q,
      O => data_out_2_MC_Q
    );
  data_out_2_MC_REG : X_BUF
    port map (
      I => data_out_2_MC_D,
      O => data_out_2_MC_Q_tsim_ireg_Q
    );
  data_out_2_MC_D1_PT_0_117 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => fout,
      O => data_out_2_MC_D1_PT_0
    );
  data_out_2_MC_D1_118 : X_OR2
    port map (
      I0 => data_out_2_MC_D1_PT_0,
      I1 => data_out_2_MC_D1_PT_0,
      O => data_out_2_MC_D1
    );
  data_out_2_MC_D2_119 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => data_out_2_MC_D2
    );
  data_out_2_MC_XOR : X_XOR2
    port map (
      I0 => data_out_2_MC_D1,
      I1 => data_out_2_MC_D2,
      O => data_out_2_MC_D
    );
  fout_120 : X_BUF
    port map (
      I => fout_MC_Q,
      O => fout
    );
  fout_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => fout_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => fout_MC_Q
    );
  fout_MC_D1_121 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => fout_MC_D1
    );
  fout_MC_D2_PT_0_122 : X_AND2
    port map (
      I0 => NlwInverterSignal_fout_MC_D2_PT_0_IN0,
      I1 => fout,
      O => fout_MC_D2_PT_0
    );
  fout_MC_D2_PT_1_123 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => jin,
      I5 => NlwInverterSignal_fout_MC_D2_PT_1_IN5,
      O => fout_MC_D2_PT_1
    );
  fout_MC_D2_PT_2_124 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_fout_MC_D2_PT_2_IN3,
      I4 => NlwInverterSignal_fout_MC_D2_PT_2_IN4,
      I5 => fin,
      O => fout_MC_D2_PT_2
    );
  fout_MC_D2_PT_3_125 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => jin,
      I4 => N_PZ_88,
      I5 => NlwInverterSignal_fout_MC_D2_PT_3_IN5,
      O => fout_MC_D2_PT_3
    );
  fout_MC_D2_PT_4_126 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_fout_MC_D2_PT_4_IN3,
      I4 => NlwInverterSignal_fout_MC_D2_PT_4_IN4,
      I5 => fin,
      O => fout_MC_D2_PT_4
    );
  fout_MC_D2_PT_5_127 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => NlwInverterSignal_fout_MC_D2_PT_5_IN4,
      I5 => N_PZ_88,
      I6 => gin,
      O => fout_MC_D2_PT_5
    );
  fout_MC_D2_PT_6_128 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_fout_MC_D2_PT_6_IN3,
      I4 => jin,
      I5 => NlwInverterSignal_fout_MC_D2_PT_6_IN5,
      I6 => NlwInverterSignal_fout_MC_D2_PT_6_IN6,
      O => fout_MC_D2_PT_6
    );
  fout_MC_D2_129 : X_OR7
    port map (
      I0 => fout_MC_D2_PT_0,
      I1 => fout_MC_D2_PT_1,
      I2 => fout_MC_D2_PT_2,
      I3 => fout_MC_D2_PT_3,
      I4 => fout_MC_D2_PT_4,
      I5 => fout_MC_D2_PT_5,
      I6 => fout_MC_D2_PT_6,
      O => fout_MC_D2
    );
  fout_MC_XOR : X_XOR2
    port map (
      I0 => fout_MC_D1,
      I1 => fout_MC_D2,
      O => fout_MC_D
    );
  data_out_3_Q : X_BUF
    port map (
      I => data_out_3_MC_Q,
      O => data_out(3)
    );
  data_out_3_MC_Q_130 : X_BUF
    port map (
      I => data_out_3_MC_Q_tsim_ireg_Q,
      O => data_out_3_MC_Q
    );
  data_out_3_MC_REG : X_BUF
    port map (
      I => data_out_3_MC_D,
      O => data_out_3_MC_Q_tsim_ireg_Q
    );
  data_out_3_MC_D1_PT_0_131 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => eout,
      O => data_out_3_MC_D1_PT_0
    );
  data_out_3_MC_D1_132 : X_OR2
    port map (
      I0 => data_out_3_MC_D1_PT_0,
      I1 => data_out_3_MC_D1_PT_0,
      O => data_out_3_MC_D1
    );
  data_out_3_MC_D2_133 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => data_out_3_MC_D2
    );
  data_out_3_MC_XOR : X_XOR2
    port map (
      I0 => data_out_3_MC_D1,
      I1 => data_out_3_MC_D2,
      O => data_out_3_MC_D
    );
  eout_134 : X_BUF
    port map (
      I => eout_MC_Q,
      O => eout
    );
  eout_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => eout_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => eout_MC_Q
    );
  eout_MC_D1_135 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => eout_MC_D1
    );
  eout_MC_D2_PT_0_136 : X_AND2
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_0_IN0,
      I1 => eout,
      O => eout_MC_D2_PT_0
    );
  eout_MC_D2_PT_1_137 : X_AND5
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => N_PZ_88,
      I4 => N_PZ_176,
      O => eout_MC_D2_PT_1
    );
  eout_MC_D2_PT_2_138 : X_AND7
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_2_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => cin,
      I5 => N_PZ_143,
      I6 => NlwInverterSignal_eout_MC_D2_PT_2_IN6,
      O => eout_MC_D2_PT_2
    );
  eout_MC_D2_PT_3_139 : X_AND7
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_3_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => ein,
      I5 => NlwInverterSignal_eout_MC_D2_PT_3_IN5,
      I6 => N_PZ_147,
      O => eout_MC_D2_PT_3
    );
  eout_MC_D2_PT_4_140 : X_AND7
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_4_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => iin,
      I5 => N_PZ_143,
      I6 => N_PZ_147,
      O => eout_MC_D2_PT_4
    );
  eout_MC_D2_PT_5_141 : X_AND7
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_5_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => ein,
      I5 => N_PZ_176,
      I6 => NlwInverterSignal_eout_MC_D2_PT_5_IN6,
      O => eout_MC_D2_PT_5
    );
  eout_MC_D2_PT_6_142 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => din,
      I4 => ein,
      I5 => N_PZ_143,
      I6 => NlwInverterSignal_eout_MC_D2_PT_6_IN6,
      O => eout_MC_D2_PT_6
    );
  eout_MC_D2_PT_7_143 : X_AND8
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_7_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => din,
      I5 => ein,
      I6 => NlwInverterSignal_eout_MC_D2_PT_7_IN6,
      I7 => NlwInverterSignal_eout_MC_D2_PT_7_IN7,
      O => eout_MC_D2_PT_7
    );
  eout_MC_D2_PT_8_144 : X_AND8
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_8_IN0,
      I1 => dec_8b10b_prs_state_ffd1,
      I2 => dec_8b10b_prs_state_ffd2,
      I3 => rst_II_UIM,
      I4 => din,
      I5 => NlwInverterSignal_eout_MC_D2_PT_8_IN5,
      I6 => NlwInverterSignal_eout_MC_D2_PT_8_IN6,
      I7 => N_PZ_147,
      O => eout_MC_D2_PT_8
    );
  eout_MC_D2_PT_9_145 : X_AND8
    port map (
      I0 => NlwInverterSignal_eout_MC_D2_PT_9_IN0,
      I1 => dec_8b10b_