decoder_time_post.vhd

8b10b design reference

      O => hout_MC_D2
    );
  hout_MC_XOR : X_XOR2
    port map (
      I0 => hout_MC_D1,
      I1 => hout_MC_D2,
      O => hout_MC_D
    );
  hin_58 : X_BUF
    port map (
      I => hin_MC_Q,
      O => hin
    );
  hin_MC_REG : X_BUF
    port map (
      I => hin_MC_D,
      O => hin_MC_Q
    );
  hin_MC_D1_PT_0_59 : X_AND3
    port map (
      I0 => data_in_1_II_UIM,
      I1 => NlwInverterSignal_hin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => hin_MC_D1_PT_0
    );
  hin_MC_D1_60 : X_OR2
    port map (
      I0 => hin_MC_D1_PT_0,
      I1 => hin_MC_D1_PT_0,
      O => hin_MC_D1
    );
  hin_MC_D2_61 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => hin_MC_D2
    );
  hin_MC_XOR : X_XOR2
    port map (
      I0 => hin_MC_D1,
      I1 => hin_MC_D2,
      O => hin_MC_D
    );
  data_in_1_II_UIM_62 : X_BUF
    port map (
      I => data_in(1),
      O => data_in_1_II_UIM
    );
  jin_63 : X_BUF
    port map (
      I => jin_MC_Q,
      O => jin
    );
  jin_MC_REG : X_BUF
    port map (
      I => jin_MC_D,
      O => jin_MC_Q
    );
  jin_MC_D1_PT_0_64 : X_AND3
    port map (
      I0 => data_in_0_II_UIM,
      I1 => NlwInverterSignal_jin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => jin_MC_D1_PT_0
    );
  jin_MC_D1_65 : X_OR2
    port map (
      I0 => jin_MC_D1_PT_0,
      I1 => jin_MC_D1_PT_0,
      O => jin_MC_D1
    );
  jin_MC_D2_66 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => jin_MC_D2
    );
  jin_MC_XOR : X_XOR2
    port map (
      I0 => jin_MC_D1,
      I1 => jin_MC_D2,
      O => jin_MC_D
    );
  data_in_0_II_UIM_67 : X_BUF
    port map (
      I => data_in(0),
      O => data_in_0_II_UIM
    );
  N_PZ_88_68 : X_BUF
    port map (
      I => N_PZ_88_MC_Q,
      O => N_PZ_88
    );
  N_PZ_88_MC_REG : X_BUF
    port map (
      I => N_PZ_88_MC_D,
      O => N_PZ_88_MC_Q
    );
  N_PZ_88_MC_D1_PT_0_69 : X_AND4
    port map (
      I0 => NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN1,
      I2 => NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN2,
      I3 => NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN3,
      O => N_PZ_88_MC_D1_PT_0
    );
  N_PZ_88_MC_D1_70 : X_OR2
    port map (
      I0 => N_PZ_88_MC_D1_PT_0,
      I1 => N_PZ_88_MC_D1_PT_0,
      O => N_PZ_88_MC_D1
    );
  N_PZ_88_MC_D2_71 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_88_MC_D2
    );
  N_PZ_88_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_88_MC_D1,
      I1 => N_PZ_88_MC_D2,
      O => N_PZ_88_MC_D
    );
  din_72 : X_BUF
    port map (
      I => din_MC_Q,
      O => din
    );
  din_MC_REG : X_BUF
    port map (
      I => din_MC_D,
      O => din_MC_Q
    );
  din_MC_D1_PT_0_73 : X_AND3
    port map (
      I0 => data_in_6_II_UIM,
      I1 => NlwInverterSignal_din_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => din_MC_D1_PT_0
    );
  din_MC_D1_74 : X_OR2
    port map (
      I0 => din_MC_D1_PT_0,
      I1 => din_MC_D1_PT_0,
      O => din_MC_D1
    );
  din_MC_D2_75 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => din_MC_D2
    );
  din_MC_XOR : X_XOR2
    port map (
      I0 => din_MC_D1,
      I1 => din_MC_D2,
      O => din_MC_D
    );
  data_in_6_II_UIM_76 : X_BUF
    port map (
      I => data_in(6),
      O => data_in_6_II_UIM
    );
  iin_77 : X_BUF
    port map (
      I => iin_MC_Q,
      O => iin
    );
  iin_MC_REG : X_BUF
    port map (
      I => iin_MC_D,
      O => iin_MC_Q
    );
  iin_MC_D1_PT_0_78 : X_AND3
    port map (
      I0 => data_in_4_II_UIM,
      I1 => NlwInverterSignal_iin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => iin_MC_D1_PT_0
    );
  iin_MC_D1_79 : X_OR2
    port map (
      I0 => iin_MC_D1_PT_0,
      I1 => iin_MC_D1_PT_0,
      O => iin_MC_D1
    );
  iin_MC_D2_80 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => iin_MC_D2
    );
  iin_MC_XOR : X_XOR2
    port map (
      I0 => iin_MC_D1,
      I1 => iin_MC_D2,
      O => iin_MC_D
    );
  data_in_4_II_UIM_81 : X_BUF
    port map (
      I => data_in(4),
      O => data_in_4_II_UIM
    );
  cin_82 : X_BUF
    port map (
      I => cin_MC_Q,
      O => cin
    );
  cin_MC_REG : X_BUF
    port map (
      I => cin_MC_D,
      O => cin_MC_Q
    );
  cin_MC_D1_PT_0_83 : X_AND3
    port map (
      I0 => data_in_7_II_UIM,
      I1 => NlwInverterSignal_cin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => cin_MC_D1_PT_0
    );
  cin_MC_D1_84 : X_OR2
    port map (
      I0 => cin_MC_D1_PT_0,
      I1 => cin_MC_D1_PT_0,
      O => cin_MC_D1
    );
  cin_MC_D2_85 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => cin_MC_D2
    );
  cin_MC_XOR : X_XOR2
    port map (
      I0 => cin_MC_D1,
      I1 => cin_MC_D2,
      O => cin_MC_D
    );
  data_in_7_II_UIM_86 : X_BUF
    port map (
      I => data_in(7),
      O => data_in_7_II_UIM
    );
  ein_87 : X_BUF
    port map (
      I => ein_MC_Q,
      O => ein
    );
  ein_MC_REG : X_BUF
    port map (
      I => ein_MC_D,
      O => ein_MC_Q
    );
  ein_MC_D1_PT_0_88 : X_AND3
    port map (
      I0 => data_in_5_II_UIM,
      I1 => NlwInverterSignal_ein_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => ein_MC_D1_PT_0
    );
  ein_MC_D1_89 : X_OR2
    port map (
      I0 => ein_MC_D1_PT_0,
      I1 => ein_MC_D1_PT_0,
      O => ein_MC_D1
    );
  ein_MC_D2_90 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => ein_MC_D2
    );
  ein_MC_XOR : X_XOR2
    port map (
      I0 => ein_MC_D1,
      I1 => ein_MC_D2,
      O => ein_MC_D
    );
  data_in_5_II_UIM_91 : X_BUF
    port map (
      I => data_in(5),
      O => data_in_5_II_UIM
    );
  gin_92 : X_BUF
    port map (
      I => gin_MC_Q,
      O => gin
    );
  gin_MC_REG : X_BUF
    port map (
      I => gin_MC_D,
      O => gin_MC_Q
    );
  gin_MC_D1_PT_0_93 : X_AND3
    port map (
      I0 => data_in_2_II_UIM,
      I1 => NlwInverterSignal_gin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => gin_MC_D1_PT_0
    );
  gin_MC_D1_94 : X_OR2
    port map (
      I0 => gin_MC_D1_PT_0,
      I1 => gin_MC_D1_PT_0,
      O => gin_MC_D1
    );
  gin_MC_D2_95 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => gin_MC_D2
    );
  gin_MC_XOR : X_XOR2
    port map (
      I0 => gin_MC_D1,
      I1 => gin_MC_D2,
      O => gin_MC_D
    );
  data_in_2_II_UIM_96 : X_BUF
    port map (
      I => data_in(2),
      O => data_in_2_II_UIM
    );
  fin_97 : X_BUF
    port map (
      I => fin_MC_Q,
      O => fin
    );
  fin_MC_REG : X_BUF
    port map (
      I => fin_MC_D,
      O => fin_MC_Q
    );
  fin_MC_D1_PT_0_98 : X_AND3
    port map (
      I0 => data_in_3_II_UIM,
      I1 => NlwInverterSignal_fin_MC_D1_PT_0_IN1,
      I2 => prs_state_fft1,
      O => fin_MC_D1_PT_0
    );
  fin_MC_D1_99 : X_OR2
    port map (
      I0 => fin_MC_D1_PT_0,
      I1 => fin_MC_D1_PT_0,
      O => fin_MC_D1
    );
  fin_MC_D2_100 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => fin_MC_D2
    );
  fin_MC_XOR : X_XOR2
    port map (
      I0 => fin_MC_D1,
      I1 => fin_MC_D2,
      O => fin_MC_D
    );
  data_in_3_II_UIM_101 : X_BUF
    port map (
      I => data_in(3),
      O => data_in_3_II_UIM
    );
  data_out_1_Q : X_BUF
    port map (
      I => data_out_1_MC_Q,
      O => data_out(1)
    );
  data_out_1_MC_Q_102 : X_BUF
    port map (
      I => data_out_1_MC_Q_tsim_ireg_Q,
      O => data_out_1_MC_Q
    );
  data_out_1_MC_REG : X_BUF
    port map (
      I => data_out_1_MC_D,
      O => data_out_1_MC_Q_tsim_ireg_Q
    );
  data_out_1_MC_D1_PT_0_103 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => gout,
      O => data_out_1_MC_D1_PT_0
    );
  data_out_1_MC_D1_104 : X_OR2
    port map (
      I0 => data_out_1_MC_D1_PT_0,
      I1 => data_out_1_MC_D1_PT_0,
      O => data_out_1_MC_D1
    );
  data_out_1_MC_D2_105 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => data_out_1_MC_D2
    );
  data_out_1_MC_XOR : X_XOR2
    port map (
      I0 => data_out_1_MC_D1,
      I1 => data_out_1_MC_D2,
      O => data_out_1_MC_D
    );
  gout_106 : X_BUF
    port map (
      I => gout_MC_Q,
      O => gout
    );
  gout_MC_REG : X_FF
    generic map(
      XON => FALSE