decoder_time_post.vhd

8b10b design reference

      I1 => PRLD,
      O => prs_state_fft1_MC_R_OR_PRLD
    );
  prs_state_fft1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft1_MC_R_OR_PRLD,
      O => prs_state_fft1_MC_Q
    );
  prs_state_fft1_MC_D1_15 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft1_MC_D1
    );
  prs_state_fft1_MC_D2_PT_0_16 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN2,
      O => prs_state_fft1_MC_D2_PT_0
    );
  prs_state_fft1_MC_D2_PT_1_17 : X_AND3
    port map (
      I0 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_1_IN1,
      I2 => frame_in_II_UIM,
      O => prs_state_fft1_MC_D2_PT_1
    );
  prs_state_fft1_MC_D2_18 : X_OR2
    port map (
      I0 => prs_state_fft1_MC_D2_PT_0,
      I1 => prs_state_fft1_MC_D2_PT_1,
      O => prs_state_fft1_MC_D2
    );
  prs_state_fft1_MC_D_19 : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D_TFF,
      I1 => prs_state_fft1_MC_Q,
      O => prs_state_fft1_MC_D
    );
  prs_state_fft1_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D1,
      I1 => prs_state_fft1_MC_D2,
      O => prs_state_fft1_MC_D_TFF
    );
  frame_in_II_UIM_20 : X_BUF
    port map (
      I => frame_in,
      O => frame_in_II_UIM
    );
  clk_II_FCLK_21 : X_BUF
    port map (
      I => clk,
      O => clk_II_FCLK
    );
  dec_8b10b_prs_state_ffd1_22 : X_BUF
    port map (
      I => dec_8b10b_prs_state_ffd1_MC_Q,
      O => dec_8b10b_prs_state_ffd1
    );
  dec_8b10b_prs_state_ffd1_MC_R_OR_PRLD_23 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,
      I1 => PRLD,
      O => dec_8b10b_prs_state_ffd1_MC_R_OR_PRLD
    );
  dec_8b10b_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dec_8b10b_prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => dec_8b10b_prs_state_ffd1_MC_R_OR_PRLD,
      O => dec_8b10b_prs_state_ffd1_MC_Q
    );
  dec_8b10b_prs_state_ffd1_MC_D1_24 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => dec_8b10b_prs_state_ffd1_MC_D1
    );
  dec_8b10b_prs_state_ffd1_MC_D2_PT_0_25 : X_AND2
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_0_IN1,
      O => dec_8b10b_prs_state_ffd1_MC_D2_PT_0
    );
  dec_8b10b_prs_state_ffd1_MC_D2_PT_1_26 : X_AND3
    port map (
      I0 => NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2,
      O => dec_8b10b_prs_state_ffd1_MC_D2_PT_1
    );
  dec_8b10b_prs_state_ffd1_MC_D2_27 : X_OR2
    port map (
      I0 => dec_8b10b_prs_state_ffd1_MC_D2_PT_0,
      I1 => dec_8b10b_prs_state_ffd1_MC_D2_PT_1,
      O => dec_8b10b_prs_state_ffd1_MC_D2
    );
  dec_8b10b_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => dec_8b10b_prs_state_ffd1_MC_D1,
      I1 => dec_8b10b_prs_state_ffd1_MC_D2,
      O => dec_8b10b_prs_state_ffd1_MC_D
    );
  dec_8b10b_prs_state_ffd2_28 : X_BUF
    port map (
      I => dec_8b10b_prs_state_ffd2_MC_Q,
      O => dec_8b10b_prs_state_ffd2
    );
  dec_8b10b_prs_state_ffd2_MC_R_OR_PRLD_29 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,
      I1 => PRLD,
      O => dec_8b10b_prs_state_ffd2_MC_R_OR_PRLD
    );
  dec_8b10b_prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dec_8b10b_prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => dec_8b10b_prs_state_ffd2_MC_R_OR_PRLD,
      O => dec_8b10b_prs_state_ffd2_MC_Q
    );
  dec_8b10b_prs_state_ffd2_MC_D1_30 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => dec_8b10b_prs_state_ffd2_MC_D1
    );
  dec_8b10b_prs_state_ffd2_MC_D2_PT_0_31 : X_AND2
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd1,
      O => dec_8b10b_prs_state_ffd2_MC_D2_PT_0
    );
  dec_8b10b_prs_state_ffd2_MC_D2_PT_1_32 : X_AND3
    port map (
      I0 => NlwInverterSignal_dec_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => dec_8b10b_prs_state_ffd2,
      O => dec_8b10b_prs_state_ffd2_MC_D2_PT_1
    );
  dec_8b10b_prs_state_ffd2_MC_D2_33 : X_OR2
    port map (
      I0 => dec_8b10b_prs_state_ffd2_MC_D2_PT_0,
      I1 => dec_8b10b_prs_state_ffd2_MC_D2_PT_1,
      O => dec_8b10b_prs_state_ffd2_MC_D2
    );
  dec_8b10b_prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => dec_8b10b_prs_state_ffd2_MC_D1,
      I1 => dec_8b10b_prs_state_ffd2_MC_D2,
      O => dec_8b10b_prs_state_ffd2_MC_D
    );
  err_chk_prs_state_ffd1_34 : X_BUF
    port map (
      I => err_chk_prs_state_ffd1_MC_Q,
      O => err_chk_prs_state_ffd1
    );
  err_chk_prs_state_ffd1_MC_R_OR_PRLD_35 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,
      I1 => PRLD,
      O => err_chk_prs_state_ffd1_MC_R_OR_PRLD
    );
  err_chk_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => err_chk_prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => err_chk_prs_state_ffd1_MC_R_OR_PRLD,
      O => err_chk_prs_state_ffd1_MC_Q
    );
  err_chk_prs_state_ffd1_MC_D1_36 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => err_chk_prs_state_ffd1_MC_D1
    );
  err_chk_prs_state_ffd1_MC_D2_PT_0_37 : X_AND2
    port map (
      I0 => err_chk_prs_state_ffd1,
      I1 => NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_0_IN1,
      O => err_chk_prs_state_ffd1_MC_D2_PT_0
    );
  err_chk_prs_state_ffd1_MC_D2_PT_1_38 : X_AND3
    port map (
      I0 => NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_1_IN2,
      O => err_chk_prs_state_ffd1_MC_D2_PT_1
    );
  err_chk_prs_state_ffd1_MC_D2_39 : X_OR2
    port map (
      I0 => err_chk_prs_state_ffd1_MC_D2_PT_0,
      I1 => err_chk_prs_state_ffd1_MC_D2_PT_1,
      O => err_chk_prs_state_ffd1_MC_D2
    );
  err_chk_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => err_chk_prs_state_ffd1_MC_D1,
      I1 => err_chk_prs_state_ffd1_MC_D2,
      O => err_chk_prs_state_ffd1_MC_D
    );
  err_chk_prs_state_ffd2_40 : X_BUF
    port map (
      I => err_chk_prs_state_ffd2_MC_Q,
      O => err_chk_prs_state_ffd2
    );
  err_chk_prs_state_ffd2_MC_R_OR_PRLD_41 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,
      I1 => PRLD,
      O => err_chk_prs_state_ffd2_MC_R_OR_PRLD
    );
  err_chk_prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => err_chk_prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => err_chk_prs_state_ffd2_MC_R_OR_PRLD,
      O => err_chk_prs_state_ffd2_MC_Q
    );
  err_chk_prs_state_ffd2_MC_D1_42 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => err_chk_prs_state_ffd2_MC_D1
    );
  err_chk_prs_state_ffd2_MC_D2_PT_0_43 : X_AND2
    port map (
      I0 => err_chk_prs_state_ffd1,
      I1 => err_chk_prs_state_ffd1,
      O => err_chk_prs_state_ffd2_MC_D2_PT_0
    );
  err_chk_prs_state_ffd2_MC_D2_PT_1_44 : X_AND3
    port map (
      I0 => NlwInverterSignal_err_chk_prs_state_ffd2_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => err_chk_prs_state_ffd2,
      O => err_chk_prs_state_ffd2_MC_D2_PT_1
    );
  err_chk_prs_state_ffd2_MC_D2_45 : X_OR2
    port map (
      I0 => err_chk_prs_state_ffd2_MC_D2_PT_0,
      I1 => err_chk_prs_state_ffd2_MC_D2_PT_1,
      O => err_chk_prs_state_ffd2_MC_D2
    );
  err_chk_prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => err_chk_prs_state_ffd2_MC_D1,
      I1 => err_chk_prs_state_ffd2_MC_D2,
      O => err_chk_prs_state_ffd2_MC_D
    );
  hout_46 : X_BUF
    port map (
      I => hout_MC_Q,
      O => hout
    );
  hout_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => hout_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => hout_MC_Q
    );
  hout_MC_D1_47 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => hout_MC_D1
    );
  hout_MC_D2_PT_0_48 : X_AND2
    port map (
      I0 => hout,
      I1 => NlwInverterSignal_hout_MC_D2_PT_0_IN1,
      O => hout_MC_D2_PT_0
    );
  hout_MC_D2_PT_1_49 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => NlwInverterSignal_hout_MC_D2_PT_1_IN4,
      I5 => NlwInverterSignal_hout_MC_D2_PT_1_IN5,
      O => hout_MC_D2_PT_1
    );
  hout_MC_D2_PT_2_50 : X_AND6
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_hout_MC_D2_PT_2_IN3,
      I4 => jin,
      I5 => N_PZ_88,
      O => hout_MC_D2_PT_2
    );
  hout_MC_D2_PT_3_51 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => jin,
      I5 => gin,
      I6 => NlwInverterSignal_hout_MC_D2_PT_3_IN6,
      O => hout_MC_D2_PT_3
    );
  hout_MC_D2_PT_4_52 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => NlwInverterSignal_hout_MC_D2_PT_4_IN4,
      I5 => gin,
      I6 => fin,
      O => hout_MC_D2_PT_4
    );
  hout_MC_D2_PT_5_53 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => hin,
      I4 => NlwInverterSignal_hout_MC_D2_PT_5_IN4,
      I5 => NlwInverterSignal_hout_MC_D2_PT_5_IN5,
      I6 => NlwInverterSignal_hout_MC_D2_PT_5_IN6,
      O => hout_MC_D2_PT_5
    );
  hout_MC_D2_PT_6_54 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_hout_MC_D2_PT_6_IN3,
      I4 => jin,
      I5 => gin,
      I6 => fin,
      O => hout_MC_D2_PT_6
    );
  hout_MC_D2_PT_7_55 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_hout_MC_D2_PT_7_IN3,
      I4 => jin,
      I5 => NlwInverterSignal_hout_MC_D2_PT_7_IN5,
      I6 => NlwInverterSignal_hout_MC_D2_PT_7_IN6,
      O => hout_MC_D2_PT_7
    );
  hout_MC_D2_PT_8_56 : X_AND7
    port map (
      I0 => dec_8b10b_prs_state_ffd1,
      I1 => dec_8b10b_prs_state_ffd2,
      I2 => rst_II_UIM,
      I3 => NlwInverterSignal_hout_MC_D2_PT_8_IN3,
      I4 => NlwInverterSignal_hout_MC_D2_PT_8_IN4,
      I5 => NlwInverterSignal_hout_MC_D2_PT_8_IN5,
      I6 => fin,
      O => hout_MC_D2_PT_8
    );
  hout_MC_D2_57 : X_OR16
    port map (
      I0 => hout_MC_D2_PT_0,
      I1 => hout_MC_D2_PT_1,
      I2 => hout_MC_D2_PT_2,
      I3 => hout_MC_D2_PT_3,
      I4 => hout_MC_D2_PT_4,
      I5 => hout_MC_D2_PT_5,
      I6 => hout_MC_D2_PT_6,
      I7 => hout_MC_D2_PT_7,
      I8 => hout_MC_D2_PT_8,
      I9 => GND,
      I10 => GND,
      I11 => GND,
      I12 => GND,
      I13 => GND,
      I14 => GND,
      I15 => GND,