decoder_time_post.vhd

8b10b design reference

  signal err_out_MC_D2_PT_21 : STD_LOGIC; 
  signal err_out_MC_D2 : STD_LOGIC; 
  signal frame_out_MC_Q : STD_LOGIC; 
  signal frame_out_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal frame_out_MC_D : STD_LOGIC; 
  signal frame_out_MC_D1_PT_0 : STD_LOGIC; 
  signal frame_out_MC_D1 : STD_LOGIC; 
  signal frame_out_MC_D2 : STD_LOGIC; 
  signal kout_MC_Q : STD_LOGIC; 
  signal kout_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal kout_MC_D : STD_LOGIC; 
  signal k_dec : STD_LOGIC; 
  signal kout_MC_D1_PT_0 : STD_LOGIC; 
  signal kout_MC_D1 : STD_LOGIC; 
  signal kout_MC_D2 : STD_LOGIC; 
  signal k_dec_MC_Q : STD_LOGIC; 
  signal k_dec_MC_D : STD_LOGIC; 
  signal k_dec_MC_D1 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_0 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_1 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_2 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_3 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_4 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_5 : STD_LOGIC; 
  signal k_dec_MC_D2_PT_6 : STD_LOGIC; 
  signal k_dec_MC_D2 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dec_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_err_chk_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_chk_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_hout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_hin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_jin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_88_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_din_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_iin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_cin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_ein_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_gin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_fin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_gout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_fout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_9_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_10_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_10_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_10_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_eout_MC_D2_PT_10_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_bin_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_ain_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_143_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_143_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_147_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_147_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_9_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_9_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dout_MC_D2_PT_10_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_cout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_9_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_bout_MC_D2_PT_10_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_9_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_10_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_aout_MC_D2_PT_10_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_7_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_10_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_10_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_10_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_11_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_11_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_11_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_11_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_11_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_12_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_13_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_14_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_14_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_15_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_16_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_16_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_17_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_17_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_17_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_17_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_17_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_18_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_18_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_18_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_18_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_18_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_19_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_19_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_19_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_19_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_19_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_20_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_20_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_20_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_20_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_21_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_21_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_21_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_21_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_err_out_MC_D2_PT_21_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_5_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_5_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_6_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_6_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_k_dec_MC_D2_PT_6_IN10 : STD_LOGIC; 
begin
  data_out_0_Q : X_BUF
    port map (
      I => data_out_0_MC_Q,
      O => data_out(0)
    );
  data_out_0_MC_Q_0 : X_BUF
    port map (
      I => data_out_0_MC_Q_tsim_ireg_Q,
      O => data_out_0_MC_Q
    );
  data_out_0_MC_REG : X_BUF
    port map (
      I => data_out_0_MC_D,
      O => data_out_0_MC_Q_tsim_ireg_Q
    );
  data_out_0_MC_D1_PT_0_1 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => hout,
      O => data_out_0_MC_D1_PT_0
    );
  data_out_0_MC_D1_2 : X_OR2
    port map (
      I0 => data_out_0_MC_D1_PT_0,
      I1 => data_out_0_MC_D1_PT_0,
      O => data_out_0_MC_D1
    );
  GND_ZERO : X_ZERO
    port map (
      O => GND
    );
  data_out_0_MC_D2_3 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => data_out_0_MC_D2
    );
  data_out_0_MC_XOR : X_XOR2
    port map (
      I0 => data_out_0_MC_D1,
      I1 => data_out_0_MC_D2,
      O => data_out_0_MC_D
    );
  prs_state_fft2_4 : X_BUF
    port map (
      I => prs_state_fft2_MC_Q,
      O => prs_state_fft2
    );
  prs_state_fft2_MC_R_OR_PRLD_5 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,
      I1 => PRLD,
      O => prs_state_fft2_MC_R_OR_PRLD
    );
  prs_state_fft2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft2_MC_R_OR_PRLD,
      O => prs_state_fft2_MC_Q
    );
  VCC_ONE : X_ONE
    port map (
      O => VCC
    );
  FOOBAR1_ctinst_0_6 : X_AND2
    port map (
      I0 => rst_II_UIM,
      I1 => rst_II_UIM,
      O => NlwInverterSignal_FOOBAR1_ctinst_0_OUT
    );
  rst_II_UIM_7 : X_BUF
    port map (
      I => rst,
      O => rst_II_UIM
    );
  prs_state_fft2_MC_D1_8 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft2_MC_D1
    );
  prs_state_fft2_MC_D2_PT_0_9 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_0_IN2,
      O => prs_state_fft2_MC_D2_PT_0
    );
  prs_state_fft2_MC_D2_PT_1_10 : X_AND6
    port map (
      I0 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => dec_8b10b_prs_state_ffd1,
      I3 => dec_8b10b_prs_state_ffd2,
      I4 => err_chk_prs_state_ffd1,
      I5 => err_chk_prs_state_ffd2,
      O => prs_state_fft2_MC_D2_PT_1
    );
  prs_state_fft2_MC_D2_11 : X_OR2
    port map (
      I0 => prs_state_fft2_MC_D2_PT_0,
      I1 => prs_state_fft2_MC_D2_PT_1,
      O => prs_state_fft2_MC_D2
    );
  prs_state_fft2_MC_D_12 : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D_TFF,
      I1 => prs_state_fft2_MC_Q,
      O => prs_state_fft2_MC_D
    );
  prs_state_fft2_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D1,
      I1 => prs_state_fft2_MC_D2,
      O => prs_state_fft2_MC_D_TFF
    );
  prs_state_fft1_13 : X_BUF
    port map (
      I => prs_state_fft1_MC_Q,
      O => prs_state_fft1
    );
  prs_state_fft1_MC_R_OR_PRLD_14 : X_OR2
    port map (
      I0 => FOOBAR1_ctinst_0,