8b10b.npl

8b10b design reference

JDF F
// Created by Project Navigator ver 1.0
PROJECT 8b10b
DESIGN 8b10b Normal
DEVFAM xbr
DEVFAMTIME 1040943751
DEVICE xc2c64
DEVICETIME 1040943751
DEVPKG VQ44
DEVPKGTIME 1040943751
DEVSPEED -4
DEVSPEEDTIME 315558000
FLOW XST VHDL
FLOWTIME 1040939905
STIMULUS main_tb.vhd Normal
STIMULUS tst_bench.vhd Normal
MODULE dis_gen.vhd
MODSTYLE dis_gen Normal
MODULE s_gen.vhd
MODSTYLE s_gen Normal
MODULE enc_func.vhd
MODSTYLE enc_func Normal
MODULE main_enc.vhd
MODSTYLE encoder Normal
LIBFILE pkg_convert.vhd work ***
LIBFILE pkg_spc_char.vhd work ***
[Normal]
p_ModelSimSimRunTime_tbw=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
p_PostParSimModelName=xstvhd, xbr, VHDL.t_postFitSimModel, 1040940011, ENCODER_TIME_POST
p_SimModelRenTopLevEntTo=xstvhd, xbr, VHDL.t_postFitSimModel, 1040940011, ENCODER_TIME_POST
p_VhdlSimDesignUnitName_behav=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1040940087, main_tb
p_VhdlSimDesignUnitName_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040941309, main_tb_post
_VhdlSimCustom_behav=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1040940087, func_sim.do
_VhdlSimCustom_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040941309, post_sim.do
_VhdlSimDo_behav=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1040940087, False
_VhdlSimDo_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040941309, False
[STATUS-ALL]
encoder.ngcFile=WARNINGS,1040943830
encoder.postParVHDLSimModel=WARNINGS,1040943830
[STRATEGY-LIST]
Normal=True