main_tb.vhd

8b10b design reference

-- **************************************************************
-- Owner:		Xilinx Inc.
-- File:  		main_tb.vhd
--
-- Purpose: 		Test for encoder and decoder functionality 
--			of 8 bit-wide transmission.
--	
-- Author:		Jennifer Jenkins
-- Date:		3-31-2000
--
-- ****************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity MAIN_TB is
end MAIN_TB;


architecture BEHAVIOUR of MAIN_TB is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE 			: STD_LOGIC := '0';

-- ********************* SIGNAL DECLARATIONS ************************
signal clk, rst				: STD_LOGIC;
signal data_trs, data_rcv 		: STD_LOGIC_VECTOR(7 downto 0);
signal k_char, dis_in, dis_out		: STD_LOGIC;
signal encoded_data, serial_data	: STD_LOGIC_VECTOR(9 downto 0);
signal frame_in_enc, frame_out_enc 	: STD_LOGIC;
signal frame_in_dec, frame_out_dec 	: STD_LOGIC;
signal kout, err_out			: STD_LOGIC;


-- ******************** COMPONENT DECLARATION ***********************

-- 8B/10B Encoder Function
component ENCODER
	port(
          	clk			: in STD_LOGIC;
          	rst			: in STD_LOGIC;                     
	  	data_in			: in STD_LOGIC_VECTOR(7 downto 0);   	-- Parallel byte of incoming data
	  	k_char			: in STD_LOGIC;				-- Asserted specifies the transmission of 
										-- a special character
	  	frame_in 		: in STD_LOGIC;				-- Asserted when parallel data is stable	 
	    	dis_in			: in STD_LOGIC;			   	-- Disparity in
	  	dis_out			: out STD_LOGIC;		  	-- Disparity out
	  	encoded_data		: out STD_LOGIC_VECTOR(9 downto 0);  	-- Encoded data to send out
	  	frame_out		: out STD_LOGIC);			-- Asserted when data is encoded and ready
										-- to be sent through the external serializer	  
        	
end component;


-- 8B/10B Decoder Function
component DECODER
    	port(
                clk			: in STD_LOGIC;
          	rst			: in STD_LOGIC;
        
          	-- Decoder inputs                      
	  	data_in			: in STD_LOGIC_VECTOR(9 downto 0);   	-- Parallel byte of incoming data
	  	frame_in 		: in STD_LOGIC;				-- Asserted when data stream is stable
		  	 
	  	-- Decoder outputs
	  	data_out		: out STD_LOGIC_VECTOR(7 downto 0);  	-- Decoded data to present
	  	frame_out		: out STD_LOGIC;			-- Asserted when data is encoded and ready
										-- to be sent through the external serializer	  
	  	kout			: out STD_LOGIC;			-- Asserted when transmission of 
										-- special character is detected
	  	err_out			: out STD_LOGIC);				-- Asserted when a non-valid 8B/10B data 
										-- stream is detected
end component;

  
-- 8B/10B Test Function Generator
component TST_8B10B
	port(

		clk20			: inout	STD_LOGIC;			-- Local clock to encoder & decoder @ 20MHz	
		sync_reset		: out	STD_LOGIC;			-- Control signals to encoder
		
		data_trs		: out	STD_LOGIC_VECTOR (7 downto 0);	-- Date byte to encode
		k_char			: out 	STD_LOGIC;			-- Asserted denotes special 
										-- character transmission									
		disparity		: out	STD_LOGIC;			-- Denotes incoming parity
		run_dis			: in	STD_LOGIC;			-- Running disparity
		frame_to_enc		: inout	STD_LOGIC;			-- Control to start data encoding
		frame_out_enc		: in	STD_LOGIC;			-- Asserted - done with encoding
	
		
		data_rcv		: in	STD_LOGIC_VECTOR (7 downto 0);	-- Incoming data from decoder
		frame_in_dec		: out 	STD_LOGIC;			-- Control to start decoding
		frame_out_dec		: in	STD_LOGIC;			-- Asserted => done decoding
		data_from_enc		: in 	STD_LOGIC_VECTOR (9 downto 0);	-- Data transfer from encoder
		data_to_dec		: out	STD_LOGIC_VECTOR (9 downto 0);  -- Serial data to decoder
		k_rcv			: in 	STD_LOGIC;			-- Asserted when special char detected
		err_rcv			: in 	STD_LOGIC);			-- Asserted when illegal char detected	
		
end component;


begin

	-- ***************** COMPONENT ASSIGNMENTS *********************
	ENC: ENCODER
		port map(
          		clk		=> clk,			
        		rst		=> rst,
			data_in		=> data_trs,
		  	k_char		=> k_char,
	  		frame_in 	=> frame_in_enc,	  
	  		dis_in		=> dis_in,			   	
	  		dis_out		=> dis_out,		  		
	  		encoded_data	=> encoded_data, 
	  		frame_out	=> frame_out_enc);


	DEC: DECODER	
		port map(	
			clk		=> clk,			
        		rst		=> rst,
 			data_in		=> serial_data,
			frame_in 	=> frame_in_dec,		  	 
	  		data_out	=> data_rcv,
	 		frame_out	=> frame_out_dec,			  
	  		kout		=> kout,
			err_out		=> err_out);	
     
        				
	TB: TST_8B10B
		port map(
			clk20		=> clk,
			sync_reset	=> rst,		
			data_trs	=> data_trs,
			k_char		=> k_char,										
			disparity	=> dis_in,
			run_dis		=> dis_out,
			frame_to_enc	=> frame_in_enc,
			frame_out_enc	=> frame_out_enc,
			data_rcv	=> data_rcv,
			frame_in_dec	=> frame_in_dec,
			frame_out_dec	=> frame_out_dec,
			data_from_enc	=> encoded_data,
			data_to_dec	=> serial_data,
			k_rcv		=> kout,
			err_rcv		=> err_out);
  
   
end BEHAVIOUR;