encoder_time_post.vhd

8b10b design reference

      I0 => NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_0_IN0,
      I1 => s_func_prs_state_ffd2,
      O => s_func_prs_state_ffd1_MC_D2_PT_0
    );
  s_func_prs_state_ffd1_MC_D2_PT_1_61 : X_AND4
    port map (
      I0 => NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_1_IN0,
      I1 => prs_state_ffd1,
      I2 => s_func_prs_state_ffd1,
      I3 => NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_1_IN3,
      O => s_func_prs_state_ffd1_MC_D2_PT_1
    );
  s_func_prs_state_ffd1_MC_D2_62 : X_OR2
    port map (
      I0 => s_func_prs_state_ffd1_MC_D2_PT_0,
      I1 => s_func_prs_state_ffd1_MC_D2_PT_1,
      O => s_func_prs_state_ffd1_MC_D2
    );
  s_func_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => s_func_prs_state_ffd1_MC_D1,
      I1 => s_func_prs_state_ffd1_MC_D2,
      O => s_func_prs_state_ffd1_MC_D
    );
  s_func_prs_state_ffd2_63 : X_BUF
    port map (
      I => s_func_prs_state_ffd2_MC_Q,
      O => s_func_prs_state_ffd2
    );
  s_func_prs_state_ffd2_MC_R_OR_PRLD_64 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => s_func_prs_state_ffd2_MC_R_OR_PRLD
    );
  s_func_prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => s_func_prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => s_func_prs_state_ffd2_MC_R_OR_PRLD,
      O => s_func_prs_state_ffd2_MC_Q
    );
  s_func_prs_state_ffd2_MC_D1_PT_0_65 : X_AND6
    port map (
      I0 => enc_8b10b_prs_state_ffd2,
      I1 => NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN1,
      I2 => NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN2,
      I3 => NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN3,
      I4 => NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN4,
      I5 => NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN5,
      O => s_func_prs_state_ffd2_MC_D1_PT_0
    );
  s_func_prs_state_ffd2_MC_D1_66 : X_OR2
    port map (
      I0 => s_func_prs_state_ffd2_MC_D1_PT_0,
      I1 => s_func_prs_state_ffd2_MC_D1_PT_0,
      O => s_func_prs_state_ffd2_MC_D1
    );
  s_func_prs_state_ffd2_MC_D2_67 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => s_func_prs_state_ffd2_MC_D2
    );
  s_func_prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => s_func_prs_state_ffd2_MC_D1,
      I1 => s_func_prs_state_ffd2_MC_D2,
      O => s_func_prs_state_ffd2_MC_D
    );
  N_PZ_168_68 : X_BUF
    port map (
      I => N_PZ_168_MC_Q,
      O => N_PZ_168
    );
  N_PZ_168_MC_REG : X_BUF
    port map (
      I => N_PZ_168_MC_D,
      O => N_PZ_168_MC_Q
    );
  N_PZ_168_MC_D1_PT_0_69 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_168_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_N_PZ_168_MC_D1_PT_0_IN1,
      O => N_PZ_168_MC_D1_PT_0
    );
  N_PZ_168_MC_D1_70 : X_OR2
    port map (
      I0 => N_PZ_168_MC_D1_PT_0,
      I1 => N_PZ_168_MC_D1_PT_0,
      O => N_PZ_168_MC_D1
    );
  N_PZ_168_MC_D2_71 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_168_MC_D2
    );
  N_PZ_168_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_168_MC_D1,
      I1 => N_PZ_168_MC_D2,
      O => N_PZ_168_MC_D
    );
  nds6_72 : X_BUF
    port map (
      I => nds6_MC_Q,
      O => nds6
    );
  nds6_MC_REG : X_BUF
    port map (
      I => nds6_MC_D,
      O => nds6_MC_Q
    );
  nds6_MC_D1_73 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => nds6_MC_D1
    );
  nds6_MC_D2_PT_0_74 : X_AND2
    port map (
      I0 => NlwInverterSignal_nds6_MC_D2_PT_0_IN0,
      I1 => N_PZ_164,
      O => nds6_MC_D2_PT_0
    );
  nds6_MC_D2_PT_1_75 : X_AND4
    port map (
      I0 => NlwInverterSignal_nds6_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_nds6_MC_D2_PT_1_IN1,
      I2 => NlwInverterSignal_nds6_MC_D2_PT_1_IN2,
      I3 => NlwInverterSignal_nds6_MC_D2_PT_1_IN3,
      O => nds6_MC_D2_PT_1
    );
  nds6_MC_D2_PT_2_76 : X_AND5
    port map (
      I0 => NlwInverterSignal_nds6_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_nds6_MC_D2_PT_2_IN1,
      I2 => NlwInverterSignal_nds6_MC_D2_PT_2_IN2,
      I3 => data_in_3_II_UIM,
      I4 => NlwInverterSignal_nds6_MC_D2_PT_2_IN4,
      O => nds6_MC_D2_PT_2
    );
  nds6_MC_D2_PT_3_77 : X_AND6
    port map (
      I0 => data_in_0_II_UIM,
      I1 => data_in_1_II_UIM,
      I2 => data_in_2_II_UIM,
      I3 => data_in_3_II_UIM,
      I4 => NlwInverterSignal_nds6_MC_D2_PT_3_IN4,
      I5 => NlwInverterSignal_nds6_MC_D2_PT_3_IN5,
      O => nds6_MC_D2_PT_3
    );
  nds6_MC_D2_78 : X_OR4
    port map (
      I0 => nds6_MC_D2_PT_0,
      I1 => nds6_MC_D2_PT_1,
      I2 => nds6_MC_D2_PT_2,
      I3 => nds6_MC_D2_PT_3,
      O => nds6_MC_D2
    );
  nds6_MC_XOR : X_XOR2
    port map (
      I0 => nds6_MC_D1,
      I1 => nds6_MC_D2,
      O => nds6_MC_D
    );
  N_PZ_164_79 : X_BUF
    port map (
      I => N_PZ_164_MC_Q,
      O => N_PZ_164
    );
  N_PZ_164_MC_REG : X_BUF
    port map (
      I => N_PZ_164_MC_D,
      O => N_PZ_164_MC_Q
    );
  N_PZ_164_MC_D1_PT_0_80 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_164_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_N_PZ_164_MC_D1_PT_0_IN1,
      O => N_PZ_164_MC_D1_PT_0
    );
  N_PZ_164_MC_D1_81 : X_OR2
    port map (
      I0 => N_PZ_164_MC_D1_PT_0,
      I1 => N_PZ_164_MC_D1_PT_0,
      O => N_PZ_164_MC_D1
    );
  N_PZ_164_MC_D2_82 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_164_MC_D2
    );
  N_PZ_164_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_164_MC_D1,
      I1 => N_PZ_164_MC_D2,
      O => N_PZ_164_MC_D
    );
  data_in_3_II_UIM_83 : X_BUF
    port map (
      I => data_in(3),
      O => data_in_3_II_UIM
    );
  data_in_4_II_UIM_84 : X_BUF
    port map (
      I => data_in(4),
      O => data_in_4_II_UIM
    );
  N_PZ_184_85 : X_BUF
    port map (
      I => N_PZ_184_MC_Q,
      O => N_PZ_184
    );
  N_PZ_184_MC_REG : X_BUF
    port map (
      I => N_PZ_184_MC_D,
      O => N_PZ_184_MC_Q
    );
  N_PZ_184_MC_D1_86 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_184_MC_D1
    );
  N_PZ_184_MC_D2_PT_0_87 : X_AND2
    port map (
      I0 => data_in_0_II_UIM,
      I1 => data_in_1_II_UIM,
      O => N_PZ_184_MC_D2_PT_0
    );
  N_PZ_184_MC_D2_PT_1_88 : X_AND2
    port map (
      I0 => data_in_0_II_UIM,
      I1 => data_in_2_II_UIM,
      O => N_PZ_184_MC_D2_PT_1
    );
  N_PZ_184_MC_D2_PT_2_89 : X_AND2
    port map (
      I0 => data_in_1_II_UIM,
      I1 => data_in_2_II_UIM,
      O => N_PZ_184_MC_D2_PT_2
    );
  N_PZ_184_MC_D2_90 : X_OR3
    port map (
      I0 => N_PZ_184_MC_D2_PT_0,
      I1 => N_PZ_184_MC_D2_PT_1,
      I2 => N_PZ_184_MC_D2_PT_2,
      O => N_PZ_184_MC_D2
    );
  N_PZ_184_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_184_MC_D1,
      I1 => N_PZ_184_MC_D2,
      O => N_PZ_184_MC_D
    );
  data_in_0_II_UIM_91 : X_BUF
    port map (
      I => data_in(0),
      O => data_in_0_II_UIM
    );
  data_in_1_II_UIM_92 : X_BUF
    port map (
      I => data_in(1),
      O => data_in_1_II_UIM
    );
  data_in_2_II_UIM_93 : X_BUF
    port map (
      I => data_in(2),
      O => data_in_2_II_UIM
    );
  pds6_94 : X_BUF
    port map (
      I => pds6_MC_Q,
      O => pds6
    );
  pds6_MC_REG : X_BUF
    port map (
      I => pds6_MC_D,
      O => pds6_MC_Q
    );
  pds6_MC_D1_95 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => pds6_MC_D1
    );
  pds6_MC_D2_PT_0_96 : X_AND2
    port map (
      I0 => NlwInverterSignal_pds6_MC_D2_PT_0_IN0,
      I1 => k_char_II_UIM,
      O => pds6_MC_D2_PT_0
    );
  pds6_MC_D2_PT_1_97 : X_AND5
    port map (
      I0 => data_in_3_II_UIM,
      I1 => data_in_4_II_UIM,
      I2 => NlwInverterSignal_pds6_MC_D2_PT_1_IN2,
      I3 => NlwInverterSignal_pds6_MC_D2_PT_1_IN3,
      I4 => N_PZ_184,
      O => pds6_MC_D2_PT_1
    );
  pds6_MC_D2_PT_2_98 : X_AND7
    port map (
      I0 => data_in_0_II_UIM,
      I1 => data_in_1_II_UIM,
      I2 => data_in_2_II_UIM,
      I3 => NlwInverterSignal_pds6_MC_D2_PT_2_IN3,
      I4 => data_in_4_II_UIM,
      I5 => NlwInverterSignal_pds6_MC_D2_PT_2_IN5,
      I6 => NlwInverterSignal_pds6_MC_D2_PT_2_IN6,
      O => pds6_MC_D2_PT_2
    );
  pds6_MC_D2_PT_3_99 : X_AND7
    port map (
      I0 => NlwInverterSignal_pds6_MC_D2_PT_3_IN0,
      I1 => NlwInverterSignal_pds6_MC_D2_PT_3_IN1,
      I2 => NlwInverterSignal_pds6_MC_D2_PT_3_IN2,
      I3 => NlwInverterSignal_pds6_MC_D2_PT_3_IN3,
      I4 => data_in_4_II_UIM,
      I5 => NlwInverterSignal_pds6_MC_D2_PT_3_IN5,
      I6 => NlwInverterSignal_pds6_MC_D2_PT_3_IN6,
      O => pds6_MC_D2_PT_3
    );
  pds6_MC_D2_100 : X_OR4
    port map (
      I0 => pds6_MC_D2_PT_0,
      I1 => pds6_MC_D2_PT_1,
      I2 => pds6_MC_D2_PT_2,
      I3 => pds6_MC_D2_PT_3,
      O => pds6_MC_D2
    );
  pds6_MC_XOR : X_XOR2
    port map (
      I0 => pds6_MC_D1,
      I1 => pds6_MC_D2,
      O => pds6_MC_D
    );
  k_char_II_UIM_101 : X_BUF
    port map (
      I => k_char,
      O => k_char_II_UIM
    );
  N_PZ_176_102 : X_BUF
    port map (
      I => N_PZ_176_MC_Q,
      O => N_PZ_176
    );
  N_PZ_176_MC_REG : X_BUF
    port map (
      I => N_PZ_176_MC_D,
      O => N_PZ_176_MC_Q
    );
  N_PZ_176_MC_D1_103 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_176_MC_D1
    );
  N_PZ_176_MC_D2_PT_0_104 : X_AND2
    port map (
      I0 => N_PZ_164,
      I1 => N_PZ_164,
      O => N_PZ_176_MC_D2_PT_0
    );
  N_PZ_176_MC_D2_PT_1_105 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_176_MC_D2_PT_1_IN0,