encoder_time_post.vhd

8b10b design reference

      CLK => clk_II_FCLK,
      SET => GND,
      RST => dis_func_prs_state_ffd1_MC_R_OR_PRLD,
      O => dis_func_prs_state_ffd1_MC_Q
    );
  dis_func_prs_state_ffd1_MC_D1_18 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => dis_func_prs_state_ffd1_MC_D1
    );
  dis_func_prs_state_ffd1_MC_D2_PT_0_19 : X_AND2
    port map (
      I0 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_0_IN0,
      I1 => dis_func_prs_state_ffd1,
      O => dis_func_prs_state_ffd1_MC_D2_PT_0
    );
  dis_func_prs_state_ffd1_MC_D2_PT_1_20 : X_AND3
    port map (
      I0 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN1,
      I2 => prs_state_ffd1,
      O => dis_func_prs_state_ffd1_MC_D2_PT_1
    );
  dis_func_prs_state_ffd1_MC_D2_21 : X_OR2
    port map (
      I0 => dis_func_prs_state_ffd1_MC_D2_PT_0,
      I1 => dis_func_prs_state_ffd1_MC_D2_PT_1,
      O => dis_func_prs_state_ffd1_MC_D2
    );
  dis_func_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => dis_func_prs_state_ffd1_MC_D1,
      I1 => dis_func_prs_state_ffd1_MC_D2,
      O => dis_func_prs_state_ffd1_MC_D
    );
  prs_state_ffd2_22 : X_BUF
    port map (
      I => prs_state_ffd2_MC_Q,
      O => prs_state_ffd2
    );
  prs_state_ffd2_MC_R_OR_PRLD_23 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => prs_state_ffd2_MC_R_OR_PRLD
    );
  prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_ffd2_MC_R_OR_PRLD,
      O => prs_state_ffd2_MC_Q
    );
  prs_state_ffd2_MC_D1_24 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_ffd2_MC_D1
    );
  prs_state_ffd2_MC_D2_PT_0_25 : X_AND3
    port map (
      I0 => prs_state_ffd2,
      I1 => prs_state_ffd1,
      I2 => frame_in_II_UIM,
      O => prs_state_ffd2_MC_D2_PT_0
    );
  prs_state_ffd2_MC_D2_PT_1_26 : X_AND5
    port map (
      I0 => NlwInverterSignal_prs_state_ffd2_MC_D2_PT_1_IN0,
      I1 => prs_state_ffd1,
      I2 => enc_8b10b_prs_state_ffd2,
      I3 => NlwInverterSignal_prs_state_ffd2_MC_D2_PT_1_IN3,
      I4 => enc_8b10b_prs_state_ffd1,
      O => prs_state_ffd2_MC_D2_PT_1
    );
  prs_state_ffd2_MC_D2_27 : X_OR2
    port map (
      I0 => prs_state_ffd2_MC_D2_PT_0,
      I1 => prs_state_ffd2_MC_D2_PT_1,
      O => prs_state_ffd2_MC_D2
    );
  prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_ffd2_MC_D1,
      I1 => prs_state_ffd2_MC_D2,
      O => prs_state_ffd2_MC_D
    );
  prs_state_ffd1_28 : X_BUF
    port map (
      I => prs_state_ffd1_MC_Q,
      O => prs_state_ffd1
    );
  prs_state_ffd1_MC_R_OR_PRLD_29 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => prs_state_ffd1_MC_R_OR_PRLD
    );
  prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_ffd1_MC_R_OR_PRLD,
      O => prs_state_ffd1_MC_Q
    );
  prs_state_ffd1_MC_D1_30 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_ffd1_MC_D1
    );
  prs_state_ffd1_MC_D2_PT_0_31 : X_AND2
    port map (
      I0 => prs_state_ffd2,
      I1 => NlwInverterSignal_prs_state_ffd1_MC_D2_PT_0_IN1,
      O => prs_state_ffd1_MC_D2_PT_0
    );
  prs_state_ffd1_MC_D2_PT_1_32 : X_AND2
    port map (
      I0 => prs_state_ffd2,
      I1 => NlwInverterSignal_prs_state_ffd1_MC_D2_PT_1_IN1,
      O => prs_state_ffd1_MC_D2_PT_1
    );
  prs_state_ffd1_MC_D2_PT_2_33 : X_AND2
    port map (
      I0 => NlwInverterSignal_prs_state_ffd1_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_prs_state_ffd1_MC_D2_PT_2_IN1,
      O => prs_state_ffd1_MC_D2_PT_2
    );
  prs_state_ffd1_MC_D2_34 : X_OR3
    port map (
      I0 => prs_state_ffd1_MC_D2_PT_0,
      I1 => prs_state_ffd1_MC_D2_PT_1,
      I2 => prs_state_ffd1_MC_D2_PT_2,
      O => prs_state_ffd1_MC_D2
    );
  prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => NlwInverterSignal_prs_state_ffd1_MC_XOR_IN0,
      I1 => prs_state_ffd1_MC_D2,
      O => prs_state_ffd1_MC_D
    );
  frame_in_II_UIM_35 : X_BUF
    port map (
      I => frame_in,
      O => frame_in_II_UIM
    );
  clk_II_FCLK_36 : X_BUF
    port map (
      I => clk,
      O => clk_II_FCLK
    );
  rst_II_UIM_37 : X_BUF
    port map (
      I => rst,
      O => rst_II_UIM
    );
  rst_II_FSR_Q_38 : X_INV
    port map (
      I => rst,
      O => rst_II_FSR_Q
    );
  enc_8b10b_prs_state_ffd2_39 : X_BUF
    port map (
      I => enc_8b10b_prs_state_ffd2_MC_Q,
      O => enc_8b10b_prs_state_ffd2
    );
  enc_8b10b_prs_state_ffd2_MC_R_OR_PRLD_40 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => enc_8b10b_prs_state_ffd2_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_ffd2_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_ffd2_MC_Q
    );
  enc_8b10b_prs_state_ffd2_MC_D1_41 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => enc_8b10b_prs_state_ffd2_MC_D1
    );
  enc_8b10b_prs_state_ffd2_MC_D2_PT_0_42 : X_AND3
    port map (
      I0 => enc_8b10b_prs_state_ffd2,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_0_IN1,
      I2 => NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_0_IN2,
      O => enc_8b10b_prs_state_ffd2_MC_D2_PT_0
    );
  enc_8b10b_prs_state_ffd2_MC_D2_PT_1_43 : X_AND3
    port map (
      I0 => NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_1_IN1,
      I2 => enc_8b10b_prs_state_ffd1,
      O => enc_8b10b_prs_state_ffd2_MC_D2_PT_1
    );
  enc_8b10b_prs_state_ffd2_MC_D2_44 : X_OR2
    port map (
      I0 => enc_8b10b_prs_state_ffd2_MC_D2_PT_0,
      I1 => enc_8b10b_prs_state_ffd2_MC_D2_PT_1,
      O => enc_8b10b_prs_state_ffd2_MC_D2
    );
  enc_8b10b_prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_ffd2_MC_D1,
      I1 => enc_8b10b_prs_state_ffd2_MC_D2,
      O => enc_8b10b_prs_state_ffd2_MC_D
    );
  enc_8b10b_prs_state_ffd3_45 : X_BUF
    port map (
      I => enc_8b10b_prs_state_ffd3_MC_Q,
      O => enc_8b10b_prs_state_ffd3
    );
  enc_8b10b_prs_state_ffd3_MC_R_OR_PRLD_46 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => enc_8b10b_prs_state_ffd3_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_ffd3_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_ffd3_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_ffd3_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_ffd3_MC_Q
    );
  enc_8b10b_prs_state_ffd3_MC_D1_47 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => enc_8b10b_prs_state_ffd3_MC_D1
    );
  enc_8b10b_prs_state_ffd3_MC_D2_PT_0_48 : X_AND3
    port map (
      I0 => enc_8b10b_prs_state_ffd2,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_0_IN1,
      I2 => enc_8b10b_prs_state_ffd1,
      O => enc_8b10b_prs_state_ffd3_MC_D2_PT_0
    );
  enc_8b10b_prs_state_ffd3_MC_D2_PT_1_49 : X_AND5
    port map (
      I0 => NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN0,
      I1 => prs_state_ffd1,
      I2 => NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN2,
      I3 => enc_8b10b_prs_state_ffd3,
      I4 => NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN4,
      O => enc_8b10b_prs_state_ffd3_MC_D2_PT_1
    );
  enc_8b10b_prs_state_ffd3_MC_D2_50 : X_OR2
    port map (
      I0 => enc_8b10b_prs_state_ffd3_MC_D2_PT_0,
      I1 => enc_8b10b_prs_state_ffd3_MC_D2_PT_1,
      O => enc_8b10b_prs_state_ffd3_MC_D2
    );
  enc_8b10b_prs_state_ffd3_MC_XOR : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_ffd3_MC_D1,
      I1 => enc_8b10b_prs_state_ffd3_MC_D2,
      O => enc_8b10b_prs_state_ffd3_MC_D
    );
  enc_8b10b_prs_state_ffd1_51 : X_BUF
    port map (
      I => enc_8b10b_prs_state_ffd1_MC_Q,
      O => enc_8b10b_prs_state_ffd1
    );
  enc_8b10b_prs_state_ffd1_MC_R_OR_PRLD_52 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => enc_8b10b_prs_state_ffd1_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_ffd1_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_ffd1_MC_Q
    );
  enc_8b10b_prs_state_ffd1_MC_D1_53 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => enc_8b10b_prs_state_ffd1_MC_D1
    );
  enc_8b10b_prs_state_ffd1_MC_D2_PT_0_54 : X_AND5
    port map (
      I0 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN0,
      I1 => prs_state_ffd1,
      I2 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN2,
      I3 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN3,
      I4 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN4,
      O => enc_8b10b_prs_state_ffd1_MC_D2_PT_0
    );
  enc_8b10b_prs_state_ffd1_MC_D2_PT_1_55 : X_AND5
    port map (
      I0 => enc_8b10b_prs_state_ffd2,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN1,
      I2 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2,
      I3 => NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN3,
      I4 => s_func_prs_state_ffd2,
      O => enc_8b10b_prs_state_ffd1_MC_D2_PT_1
    );
  enc_8b10b_prs_state_ffd1_MC_D2_56 : X_OR2
    port map (
      I0 => enc_8b10b_prs_state_ffd1_MC_D2_PT_0,
      I1 => enc_8b10b_prs_state_ffd1_MC_D2_PT_1,
      O => enc_8b10b_prs_state_ffd1_MC_D2
    );
  enc_8b10b_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_ffd1_MC_D1,
      I1 => enc_8b10b_prs_state_ffd1_MC_D2,
      O => enc_8b10b_prs_state_ffd1_MC_D
    );
  s_func_prs_state_ffd1_57 : X_BUF
    port map (
      I => s_func_prs_state_ffd1_MC_Q,
      O => s_func_prs_state_ffd1
    );
  s_func_prs_state_ffd1_MC_R_OR_PRLD_58 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => s_func_prs_state_ffd1_MC_R_OR_PRLD
    );
  s_func_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => s_func_prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => s_func_prs_state_ffd1_MC_R_OR_PRLD,
      O => s_func_prs_state_ffd1_MC_Q
    );
  s_func_prs_state_ffd1_MC_D1_59 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => s_func_prs_state_ffd1_MC_D1
    );
  s_func_prs_state_ffd1_MC_D2_PT_0_60 : X_AND2
    port map (